AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

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ID 683707
Date 10/30/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example 2. Getting Started with the TSN for Drive-on-Chip Design Example 3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board 4. Running HPS Software for the TSN Drive-on-Chip Design 5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board 6. Running the Program 7. TSN Configuration Example 8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example A. Example .qsf for Pin Assignments and Attributes B. Top-level Verilog HDL File Example C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example x
1.1. Features of TSN for Drive-on-Chip Design Example 1.2. TSN for Drive-on-Chip Design Example General Description 1.3. Messages from the TSN Drive-on-Chip Design Example 1.4. Design Flow for the TSN Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example x
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example 2.2. Software Requirements for the TSN for Drive-on-Chip Design Example 2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example 2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example 2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.7. Configuring the TSN IP
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board x
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example 3.2. Modifying the Drive-On-Chip Qsys System 3.3. Adding the TTTech TSN IP to the Qsys system 3.4. Connecting the TSN and Drive-on-Chip Subsystems 3.5. Compiling the Quartus Prime Design and Top-Level Module 3.6. Generating the Preloader 3.7. Generating a .jic file 3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools 3.9. Launching a YOCTO Build 3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example 3.11. Changing MAC Addresses 3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design x
4.1. Installing the Arm Compiler for Motor Control from Linux 4.2. Creating a Basic C Program for Motor Control 4.3. OPC UA PubSub based on open62541 4.4. Getting and Building open62541 4.5. Setting up Debug Sessions in DS-5
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design
5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board
6. Running the Program
7. TSN Configuration Example
8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example
A. Example .qsf for Pin Assignments and Attributes
B. Top-level Verilog HDL File Example
C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example
D. Script to read and change MAC addresses from Cyclone V SoC EEPROM

3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example

  1. Change the name to differentiate the new project. For example, for the .qpf file DOC_TANDEM_CVSX_NIOS_TSN, as this variation of the project includes the drive-on-chip based on Nios II soft-processor and the TSN IP.
    You can also change the name of the .qsys file.
  2. In Intel Quartus Prime 17.0, navigate to File > Open Project and select the newly-named .qpf file.
  3. Apply the following changes;
    1. Create a new revision of the project, by selecting Project > Revisions and add a new revision based on DOC_TANDEM_MAX_10, for example DOC_TANDEM_CVSX_NIOS_TSN.
    2. Remove the previous revision.
    3. Change the target device, by selecting Assignments > Device > 5CSXFC6D6F31C6:
      Figure 5. Selected Device
  4. Change the name of the top-level Verilog HDL file from to DOC_TANDEM_MAX10.v to DOC_TANDEM_CVSX_NIOS_TSN.v
  5. In the new top-level Verilog HDL file, change the name of the main Qsys instance u-doc to match the name of the .qsys file. For example: DOC_TANDEM_CVSX_NIOS_TSN_QSYS
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