Nios® V Processor Reference Manual

ID 683632
Date 7/26/2024
Public
Document Table of Contents

3.2.1. Pipelined Architecture

The Nios® V/m processor employs a five-stage datapath.

Table 20.  Processor Pipeline Stages
Stage Denotation Function
F Instruction fetch
  • PC+4 calculation
  • Next instruction fetch
  • Pre-decode for register file read
D Instruction decode
  • Decode the instruction
  • Register file read data available
  • Hazard resolution and data forwarding
E Instruction execute
  • ALU operations
  • Memory address calculation
  • Branch resolution
  • CSR read/write
M Memory
  • Memory and multicycle operations
  • Register file write
  • Branch redirection
W Write back
  • Facilitates data dependency resolution by providing general-purpose register value.

The Nios® V/m processor implements the general-purpose register file using the M20K memory blocks. The processor takes one cycle to read from an M20K location. Therefore, the F-stage initiates register file reads so general-purpose register values are available in D-stage.

Writing to the M20K location takes two cycles. Therefore, the M-stage initiates writes to a general-purpose register. If there is a dependency to resolve, the M-stage carries forward the value to the W-stage.

The core resolves data dependencies in the D-stage. Operands can move from register file read or E-stage, M-stage, or W-stage.

Reasons for the pipeline stalling:
  • Data dependency—if the source operand is not available in the D-stage, instruction in the D-stage and F-stage stalls until the operand becomes available. This happens when the destination general-purpose register of a load or multicycle instruction in the E-stage or M-stage is the source for the instruction in the D-stage.
  • Resource stall—if a memory operation or multicycle is pending in the M-stage, the instructions in the preceding stages stall until M-stage completes the instruction.