Nios® V Processor Reference Manual

ID 683632
Date 7/26/2024
Public
Document Table of Contents

4.4.1.2. Debug Mode (D-mode)

The Debug mode (D-mode) is an additional privilege level to support off-chip debugging and manufacturing test.

The core can enter D-mode using any of the following methods:

  • After reset when bit is set in debug CSR.
  • Using debug interrupt.
  • Using EBREAK instruction when bit is set in debug CSR.
  • Using single step.