Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 7/08/2024
Public
Document Table of Contents

3.3.8. Specify Synthesis and Simulation Files in the Platform Designer Component Editor

The Files tab in the Platform Designer Component Editor allows you to specify synthesis and simulation files for your custom component.

If you already have an HDL file that describes the behavior and structure of your component, you can specify those files on the Files tab.

If you do not yet have an HDL file, you can specify the signals, interfaces, and parameters of the component in the Component Editor, and then use the Create Synthesis File from Signals option on the Files tab to create the top-level HDL file. The Component Editor generates the _hw.tcl commands to specify the files.

Note: After you analyze the component's top-level HDL file (on the Files tab), you cannot add or remove signals or change the signal names on the Signals & Interfaces tab. If you need to edit signals, edit your HDL source, and then click Create Synthesis File from Signals on the Files tab to integrate your changes.

A component uses filesets to specify the different sets of files that you can generate for an instance of the component. The supported fileset types are: QUARTUS_SYNTH, for synthesis and compilation in the Quartus® Prime software, SIM_VERILOG, for Verilog HDL simulation, and SIM_VHDL, for VHDL simulation.

In an _hw.tcl file, you can add a fileset with the add_fileset command. You can then list specific files with the add_fileset_file command. The add_fileset_property command allows you to add properties such as TOP_LEVEL.

You can populate a fileset with a fixed list of files, add different files based on a parameter value, or even generate an HDL file with a custom HDL generator function outside of the _hw.tcl file.