4.8.2. Reducing Power Consumption by Minimizing Toggle Rates

Quartus® Prime Pro Edition User Guide: Platform Designer

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Date 7/08/2024

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4.8.2. Reducing Power Consumption by Minimizing Toggle Rates

A Platform Designer system consumes power whenever logic transitions between on and off states. When the state is held constant between clock edges, no charging or discharging occurs. You can use the following design methodologies to reduce the toggle rates of your design:

Registering component boundaries
Using clock enable signals
Inserting bridges

Platform Designer interconnect is uniquely combinational when no adapters or bridges are present and there is no interconnect pipelining. When an agent interface is not selected by a host, various signals may toggle and propagate into the component. By registering the boundary of your component at the host or agent interface, you can minimize the toggling of the interconnect and your component. In addition, registering boundaries can improve operating frequency. When you register the signals at the interface level, you must ensure that the component continues to operate within the interface standard specification.

Avalon® memory mapped waitrequest is a difficult signal to synchronize when you add registers to your component. The waitrequest signal must be asserted during the same clock cycle that a host asserts read or write to in order to prolong the transfer. A host interface can read the waitrequest signal too early and post more reads and writes prematurely.

Note:

There is no direct AXI equivalent for waitrequest and burstcount, though the AMBA Protocol Specification implies that the AXI ready signal cannot depend combinationally on the AXI valid signal. Therefore, Platform Designer typically buffers AXI component boundaries for the ready signal.

For agent interfaces, the interconnect manages the begintransfer signal, which is asserted during the first clock cycle of any read or write transfer. If the waitrequest is one clock cycle late, you can logically OR the waitrequest and the begintransfer signals to form a new waitrequest signal that is properly synchronized. Alternatively, the component can assert waitrequest before it is selected, guaranteeing that the waitrequest is already asserted during the first clock cycle of a transfer.

Figure 180. Variable Latency

Using Clock Enables

You can use clock enables to hold the logic in a steady state, and the write and read signals as clock enables for agent components. Even if you add registers to your component boundaries, the interface can potentially toggle without the use of clock enables. You can also use the clock enable to disable combinational portions of the component.

For example, you can use an active high clock enable to mask the inputs into the combinational logic to prevent it from toggling when the component is inactive. Before preventing inactive logic from toggling, you must determine if the masking causes the circuit to function differently. If masking causes a functional failure, it may be possible to use a register stage to hold the combinational logic constant between clock cycles.

Inserting Bridges

You can use bridges to reduce toggle rates, if you do not want to modify the component by using boundary registers or clock enables. A bridge acts as a repeater where transfers to the agent interface are repeated on the host interface. If the bridge is not accessed, the components connected to its host interface are also not accessed. The host interface of the bridge remains idle until a host accesses the bridge agent interface.

Bridges can also reduce the toggle rates of signals that are inputs to other host interfaces. These signals are typically readdata, readdatavalid, and waitrequest. Subordinate interfaces that support read accesses drive the readdata, readdatavalid, and waitrequest signals. A bridge inserts either a register or clock crossing FIFO between the agent interface and the host to reduce the toggle rate of the host input signals.

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Quartus® Prime Pro Edition User Guide: Platform Designer

4.8.2. Reducing Power Consumption by Minimizing Toggle Rates

Using Clock Enables

Inserting Bridges