Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 7/08/2024
Public
Document Table of Contents

1.16.1. Generation Dialog Box Options

Platform Designer system generation creates files for Quartus® Prime synthesis and supported third-party simulators. The Generation dialog box appears when you click Generate HDL, or when you attempt to close a system prior to generation.

By default, the synthesis and simulation files generate into the Platform Designer project directory.

You can specify the following system generation options in the Generation dialog box:

Table 19.   Generation Dialog Box Options
Option Description
Create HDL design files for synthesis Allows you to specify Verilog or VHDL file type generation for the system's top-level definition and child instances. Select None to skip generation of synthesis files.
Create timing and resource estimates for each IP in your system to be used with third-party synthesis tools Generates a non-functional Verilog Design File (.v) for use by supported third-party EDA synthesis tools. Estimates timing and resource usage for the IP component. The generated netlist file name is <ip_component_name>_syn.v.
Create Block Symbol File (.bsf) Generates a Block Symbol File (.bsf) for use in a larger system schematic Block Diagram File (.bdf).
IP-XACT Generates an IP-XACT file for the system, and adds the file to the IP Catalog.
Note: Platform Designer supports importing and exporting files in IP-XACT 2009 format and exporting IP-XACT files in 2014 format.
Generate IP Core Documentation Generates the IP user guide documentation for the components in your system (when available).
Create simulation model Generates Verilog HDL or VHDL simulation models and simulator setup scripts. Enable the checkbox for one or more simulators to generate setup scripts for those tools in the following location:
<top-level system name>/<system name>/<sim>/<simulator>
If you do not specify a simulator, the setup scripts generate for all supported tools.
Clear output directories for selected generation targets Clears previous synthesis and simulation file generation data for the current system.
Use multiple processors for faster IP generation (when available) Disables or enables parallel IP generation for faster IP generation using multiple processors when available in your system.
Note: The Questa* Intel® FPGA Edition simulator supports native, mixed-language (VHDL, Verilog HDL, SystemVerilog) simulation. Therefore, Intel simulation libraries may not be compatible with single language simulators. If you have a VHDL-only license, some versions of ModelSim* simulators may not support simulation for IPs written in Verilog. As a workaround, you can use the Questa* Intel® FPGA Edition simulator, or purchase a mixed-language simulation license from Siemens EDA.