Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 7/08/2024
Public
Document Table of Contents

5.1. Memory-Mapped Interfaces

Platform Designer supports the implementation of memory-mapped interfaces for Avalon® , AXI, and APB protocols.

Platform Designer interconnect transmits memory-mapped transactions between hosts and agents in packets. The command network transports read and write packets from host interfaces to agent interfaces. The response network transports response packets from agent interfaces to host interfaces.

For each component interface, Platform Designer interconnect manages memory-mapped transfers and interacts with signals on the connected interface. Host and agent interfaces can implement different signals based on interface parameterizations, and Platform Designer interconnect provides any necessary adaptation between them. In the path between host and agents, Platform Designer interconnect may introduce registers for timing synchronization, finite state machines for event sequencing, or nothing at all, depending on the services required by the interfaces.

Platform Designer interconnect supports the following implementation scenarios:

  • Any number of components with host and agent interfaces. The host‑to‑agent relationship can be one‑to‑one, one‑to‑many, many‑to‑one, or many‑to‑many.
  • Hosts and agents of different data widths.
  • Hosts and agents operating in different clock domains.
  • IP Components with different interface properties and signals. Platform Designer adapts the component interfaces so that interfaces with the following differences can be connected:
    • Avalon® and AXI interfaces that use active‑high and active‑low signaling. AXI signals are active high, except for the reset signal.
    • Interfaces with different burst characteristics.
    • Interfaces with different latencies.
    • Interfaces with different data widths.
    • Interfaces with different optional interface signals.
      Note: Since interface connections between AMBA* 3 AXI and AMBA* 4 AXI declare a fixed set of signals with variable latency, there is no need for adapting between active-low and active-high signaling, burst characteristics, different latencies, or port signatures. Adaptation might be necessary between Avalon® interfaces.

In this example, there are two components hosting the system, a processor and a DMA controller, each with two host interfaces. The hosts connect through the Platform Designer interconnect to agents in the Platform Designer system.

The dark blue blocks represent interconnect components. The dark gray boxes indicate items outside of the Platform Designer system and the Quartus® Prime software design, and show how to export component interfaces and how to connect these interfaces to external devices.

Figure 191.  Platform Designer interconnect for an Avalon® Memory Mapped System with Multiple Hosts