Intel® Stratix® 10 SEU Mitigation User Guide

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ID 683602
Date 2/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 SEU Mitigation Overview 2. Intel® Stratix® 10 Mitigation Techniques for CRAM 3. Secure Device Manager ECC Error Detection 4. Intel® Stratix® 10 SEU Mitigation Implementation Guides 5. Advanced SEU Detection Intel® FPGA IP References 6. Intel® Stratix® 10 Fault Injection Debugger References 7. Intel® Stratix® 10 SEU Mitigation User Guide Archives 8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
1. Intel® Stratix® 10 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques for Intel® Stratix® 10 Devices 1.2. Configuration RAM 1.3. Memory Blocks Error Correction Code (ECC) Support 1.4. Secure Device Manager ECC Error 1.5. Triple-Module Redundancy 1.6. Failure Rates
2. Intel® Stratix® 10 Mitigation Techniques for CRAM x
2.1. CRAM Error Detection and Correction 2.2. Internal Scrubbing and Priority Scrubbing 2.3. SEU Sensitivity Processing 2.4. Designating the Sensitivity of the Design Hierarchy 2.5. Evaluating a System's Response to Functional Upsets
2.1. CRAM Error Detection and Correction x
2.1.1. Error Message Queue 2.1.2. SEU_ERROR Pin Behavior
2.2. Internal Scrubbing and Priority Scrubbing x
2.2.1. Internal Scrubbing 2.2.2. Priority Scrubbing
2.3. SEU Sensitivity Processing x
2.3.1. Advanced SEU Detection IP Core
2.3.1. Advanced SEU Detection IP Core x
2.3.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.3.1.2. On-Chip Lookup Sensitivity Processing 2.3.1.3. Off-Chip Lookup Sensitivity Processing 2.3.1.4. SMH Lookup
2.3.1.3. Off-Chip Lookup Sensitivity Processing x
2.3.1.3.1. Off-Chip Lookup Sensitivity Processing Operation Flow
2.3.1.4. SMH Lookup x
2.3.1.4.1. SMH Revision 4 File Format
2.4. Designating the Sensitivity of the Design Hierarchy x
2.4.1. Hierarchy Tagging
2.5. Evaluating a System's Response to Functional Upsets x
2.5.1. Intel® Quartus® Prime Fault Injection Debugger
3. Secure Device Manager ECC Error Detection x
3.1. SDM ECC Error Message Bits 3.2. SDM ECC Error Signals Behavior
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides x
4.1. Setting SEU_ERROR Pin 4.2. Intel® Quartus® Prime SEU Software Settings 4.3. Enabling Priority Scrubbing 4.4. Performing Hierarchy Tagging 4.5. Programming Sensitivity Map Header File into Memory 4.6. Performing Lookup for Sensitivity Map Header 4.7. Using the Fault Injection Debugger 4.8. Analyzing SEU Errors Using Signal Tap 4.9. Intel® Quartus® Prime Software SEU FIT Reports
4.7. Using the Fault Injection Debugger x
4.7.1. Enabling the Fault Injection Debugger 4.7.2. Launching and Setting Up the Fault Injection Debugger 4.7.3. Configuring Your Device and the Fault Injection Debugger 4.7.4. Constraining Regions for Fault Injection 4.7.5. Injecting Errors 4.7.6. Injecting Double Adjacent Errors
4.7.5. Injecting Errors x
4.7.5.1. Injecting Errors to a Random Location 4.7.5.2. Injecting Errors to a Specific Location
4.7.6. Injecting Double Adjacent Errors x
4.7.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.7.6.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.9. Intel® Quartus® Prime Software SEU FIT Reports x
4.9.1. Enabling the Projected SEU FIT by Component Usage Report 4.9.2. SEU FIT Parameters Report 4.9.3. Projected SEU FIT by Component Usage Report
4.9.3. Projected SEU FIT by Component Usage Report x
4.9.3.1. Component FIT Rates 4.9.3.2. Raw FIT 4.9.3.3. Utilized FIT 4.9.3.4. Mitigated FIT 4.9.3.5. Architectural Vulnerability Factor
4.9.3.3. Utilized FIT x
4.9.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 4.9.3.3.2. Considerations for Small Designs
5. Advanced SEU Detection Intel® FPGA IP References x
5.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.2. Advanced SEU Detection Intel® FPGA IP Ports
6. Intel® Stratix® 10 Fault Injection Debugger References x
6.1. Fault Injection Debugger Interface Parameters 6.2. Fault Injection Debugger Command-Line Interface
1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide

2.1.1. Error Message Queue

The Intel® Stratix® 10 device error message queue stores the error messages when detecting an SEU error. Each error message contains information about the sector address, error type, and error location. The error message queue is capable of storing a maximum of eight different messages. A warning message appears if the error message queue has more than eight different messages. Click Read EMR to display and clear the error message queue.

You can retrieve the contents of the error message queue using the following tools:

  • Fault Injection Debugger tool
  • Advanced SEU Detection Intel® FPGA IP
  • Mailbox command
Note: Do not use this mailbox command if your design contains the Advanced SEU Detection Intel® FPGA IP.
You may send the mailbox command via JTAG interface using Configuration Debugger Tool to retrieve the SEU error message:
  1. From the Intel® Quartus® Prime menu, select Tools > Configuration Debugger.
  2. Select the hardware in Hardware Setup and click Load Device to select your device.
  3. Click View and select SDM Tool to enable the Mailbox Client window.
  4. Specify the Command Code and Parameter List.
  5. Click Send and read the response in Session Log.
Figure 2. Executing the read_seu_error Mailbox Command via JTAG Interface Using the Configuration Debugger ToolThe figure below shows a corrected error at sector 77 in frame 9B1 and bit 594.
Table 3.  SEU Error Message Bit Description
Name Width Bit Description

Sector address

(Most significant 32-bit word in avst_seu_source_data signal

32 31:24 Reserved
23:16 Address of sector with error
15:8 Reserved
7:4 Error type:
  • 0000—SEU error
  • 0001—SDM and Subsystem ECC error
  • Remaining values—reserved
3:0 Reserved

Error location2

(Least significant 32-bit word in avst_seu_source_data signal)

32 31:29 Bit 31:29—Error type:
  • 001—single bit error
  • 011—uncorrectable multiple bits error
28 Correction Status:
  • 0=Not corrected
  • 1=Corrected
27:24 Reserved
23:12 Bit position within frame
11:0 Combined of Row and Frame index
Note: Intel® recommends that you turn on the Internal Scrubbing feature. If an error is detected in a sector, and you did not enable the Internal Scrubbing option, the SEU feature for that particular sector is turned off. Additionally, subsequent SEU occurrence in the same sector either correctable or uncorrectable error, is not detected.
Related Information
2 For single bit error with internal scrubbing, the error location provides the error bit position. For multiple bits error or single bit error without internal scrubbing, bit [23:0] returns 0.
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