Intel® Stratix® 10 SEU Mitigation User Guide

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ID 683602
Date 2/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 SEU Mitigation Overview 2. Intel® Stratix® 10 Mitigation Techniques for CRAM 3. Secure Device Manager ECC Error Detection 4. Intel® Stratix® 10 SEU Mitigation Implementation Guides 5. Advanced SEU Detection Intel® FPGA IP References 6. Intel® Stratix® 10 Fault Injection Debugger References 7. Intel® Stratix® 10 SEU Mitigation User Guide Archives 8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
1. Intel® Stratix® 10 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques for Intel® Stratix® 10 Devices 1.2. Configuration RAM 1.3. Memory Blocks Error Correction Code (ECC) Support 1.4. Secure Device Manager ECC Error 1.5. Triple-Module Redundancy 1.6. Failure Rates
2. Intel® Stratix® 10 Mitigation Techniques for CRAM x
2.1. CRAM Error Detection and Correction 2.2. Internal Scrubbing and Priority Scrubbing 2.3. SEU Sensitivity Processing 2.4. Designating the Sensitivity of the Design Hierarchy 2.5. Evaluating a System's Response to Functional Upsets
2.1. CRAM Error Detection and Correction x
2.1.1. Error Message Queue 2.1.2. SEU_ERROR Pin Behavior
2.2. Internal Scrubbing and Priority Scrubbing x
2.2.1. Internal Scrubbing 2.2.2. Priority Scrubbing
2.3. SEU Sensitivity Processing x
2.3.1. Advanced SEU Detection IP Core
2.3.1. Advanced SEU Detection IP Core x
2.3.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.3.1.2. On-Chip Lookup Sensitivity Processing 2.3.1.3. Off-Chip Lookup Sensitivity Processing 2.3.1.4. SMH Lookup
2.3.1.3. Off-Chip Lookup Sensitivity Processing x
2.3.1.3.1. Off-Chip Lookup Sensitivity Processing Operation Flow
2.3.1.4. SMH Lookup x
2.3.1.4.1. SMH Revision 4 File Format
2.4. Designating the Sensitivity of the Design Hierarchy x
2.4.1. Hierarchy Tagging
2.5. Evaluating a System's Response to Functional Upsets x
2.5.1. Intel® Quartus® Prime Fault Injection Debugger
3. Secure Device Manager ECC Error Detection x
3.1. SDM ECC Error Message Bits 3.2. SDM ECC Error Signals Behavior
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides x
4.1. Setting SEU_ERROR Pin 4.2. Intel® Quartus® Prime SEU Software Settings 4.3. Enabling Priority Scrubbing 4.4. Performing Hierarchy Tagging 4.5. Programming Sensitivity Map Header File into Memory 4.6. Performing Lookup for Sensitivity Map Header 4.7. Using the Fault Injection Debugger 4.8. Analyzing SEU Errors Using Signal Tap 4.9. Intel® Quartus® Prime Software SEU FIT Reports
4.7. Using the Fault Injection Debugger x
4.7.1. Enabling the Fault Injection Debugger 4.7.2. Launching and Setting Up the Fault Injection Debugger 4.7.3. Configuring Your Device and the Fault Injection Debugger 4.7.4. Constraining Regions for Fault Injection 4.7.5. Injecting Errors 4.7.6. Injecting Double Adjacent Errors
4.7.5. Injecting Errors x
4.7.5.1. Injecting Errors to a Random Location 4.7.5.2. Injecting Errors to a Specific Location
4.7.6. Injecting Double Adjacent Errors x
4.7.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.7.6.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.9. Intel® Quartus® Prime Software SEU FIT Reports x
4.9.1. Enabling the Projected SEU FIT by Component Usage Report 4.9.2. SEU FIT Parameters Report 4.9.3. Projected SEU FIT by Component Usage Report
4.9.3. Projected SEU FIT by Component Usage Report x
4.9.3.1. Component FIT Rates 4.9.3.2. Raw FIT 4.9.3.3. Utilized FIT 4.9.3.4. Mitigated FIT 4.9.3.5. Architectural Vulnerability Factor
4.9.3.3. Utilized FIT x
4.9.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 4.9.3.3.2. Considerations for Small Designs
5. Advanced SEU Detection Intel® FPGA IP References x
5.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.2. Advanced SEU Detection Intel® FPGA IP Ports
6. Intel® Stratix® 10 Fault Injection Debugger References x
6.1. Fault Injection Debugger Interface Parameters 6.2. Fault Injection Debugger Command-Line Interface
1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide

5.2. Advanced SEU Detection Intel® FPGA IP Ports

Figure 15.  Advanced SEU Detection Intel® FPGA IP On-Chip Sensitivity Processing Block Diagram
Table 8.   Advanced SEU Detection Intel® FPGA IP On-Chip Sensitivity Processing Ports
Ports Width Direction Description
clk 1 Input User input clock. The maximum frequency is 250 MHz.
reset 1 Input Active high, synchronous reset signal.
Note: For IP instantiation guidelines, refer to the related information about the Reset Release Intel® FPGA IP.
sys_error 1 Output Logic high indicates that there is an error in the system while retrieving the SEU error.
busy 1 Output Logic high indicates that the Advanced SEU Detection Intel® FPGA IP is busy processing the SEU data. The signal goes low when processing completes with assertion of the critical_error or noncritical_error signal.
generic_sdm_valid_out 1 Output Logic high for one clock cycle indicates that the device detects an SDM and Subsystem ECC error.
generic_sdm_data_out 64 Output Outputs the SDM ECC error message content.
critical_clear 1 Input Assert high to clear the error report (critical_error, noncritical_error, regions_report, and seu_data) for the last processed SEU data input.
critical_error 1 Output Logic high indicates that a.smh lookup determined that the SEU error is in a critical region.
noncritical_error 1 Output Logic high indicates that a .smh lookup determined that the SEU error is in a non-critical region.
seu_data 64 Output Shows the SEU error message for the last processed SEU data input. The port is available if you turn on Show raw SEU error message. For more information, refer to the related information about the error message queue.
regions_report 1–32 Output Indicates the region ID for the error as reported by the .smh lookup. The port width of this signal is set by the Largest ASD region ID used parameter.
address 32 Output Avalon® memory-mapped interface address bus in unit of Byte addressing.
read 1 Output Avalon® memory-mapped interface read control signal.
waitrequest 1 Input Avalon® memory-mapped interface wait request signal.
readdata 32 Input Avalon® memory-mapped interface data bus.
readdatavalid 1 Input Avalon® memory-mapped interface data valid signal.
seu_error_out 1 Output Signal is synchronous with the input clock of the IP. Assert high when it detects SEU.
Figure 16.  Advanced SEU Detection Intel® FPGA IP Off-Chip Sensitivity Processing Block Diagram
Table 9.   Advanced SEU Detection Intel® FPGA IP Off-Chip Sensitivity Processing Ports
Ports Width Direction Description
clk 1 Input User input clock. The maximum frequency is 250 MHz.
reset 1 Input Active high, synchronous reset signal.
Note: For IP instantiation guidelines, refer to the related information about the Reset Release Intel® FPGA IP.
sys_error 1 Output Logic high indicates that there is an error in the system while retrieving the SEU error.
generic_sdm_valid_out 1 Output Logic high for one clock cycle indicates that the device detects an SDM and Subsystem ECC error.
generic_sdm_data_out 64 Output Outputs the SDM ECC error message content.
data 64 Output Avalon® streaming interface data signal that provides SEU error message from the FIFO entry.
valid 1 Output Avalon® streaming interface data valid signal that indicates the avst_seu_source_data signal contains valid data.
ready 1 Input Avalon® streaming interface ready signal.
seu_error_out 1 Output Signal is synchronous with the input clock of the IP. Assert high when it detects SEU.
Related Information
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