Intel® Stratix® 10 SEU Mitigation User Guide

ID 683602
Date 2/20/2024
Public
Document Table of Contents

3.1. SDM ECC Error Message Bits

The SDM ECC error message bits store the error message when the Intel® Stratix® 10 device detects an SDM ECC error.

The SDM ECC error message contains information about the sector address and the type of error. You can retrieve the contents of the error message from the generic_sdm_data_out signal of the Advanced SEU Detection Intel® FPGA IP.

Table 6.  SDM and Subsystem ECC Error Message Bits Description
Name Width Bit Description

Sector address

(Most significant 32-bit word in generic_sdm_data_out signal)

32 31:24 Reserved
23:16 Address of sector with error
15:8 Reserved
7:4 Error type:
  • 0000—SEU error
  • 0001—SDM and subsystem ECC error
  • Remaining values—reserved
3:0 Reserved

Error data

(Least significant 32-bit word in generic_sdm_data_out signal)

32 31:29

SDM ECC error type:

  • 101—single bit error in transceiver tile (E-Tile)
  • 110—multiple bits error in transceiver tile (E-Tile)
28 Correction status:
  • 0—not corrected
  • 1—corrected
27:12 Reserved
11:0
Specific SDM and Subsystem ECC error type 101 details:
  • 0x2ACRE_SERDES_ECC_CODE_ONEBIT
  • 0x2BCRE_SERDES_ECC_DATA_ONEBIT
  • 0x2CCRE_SERDES_ECC_CODE_ONEBIT
  • 0x2DCRE_SERDES_ECC_DATA_ONEBIT
  • 0x2ECRE_RSFEC_ECC_ONEBIT
Specific SDM and Subsystem ECC error type 110 details:
  • 0x10CRE_SERDES_TWOBIT_ECC_CODE
  • 0x11CRE_SERDES_TWOBIT_ECC_DATA
  • 0x12CRE_SPICO_TWOBIT_ECC_CODE
  • 0x13CRE_SPICO_TWOBIT_ECC_DATA
  • 0x14CRE_RSFEC_ECC_TWOBIT
Note: For uncorrectable SDM ECC error, Intel® recommends that you reconfigure the Intel® Stratix® 10 device.