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1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
4.1. Setting SEU_ERROR Pin
4.2. Intel® Quartus® Prime SEU Software Settings
4.3. Enabling Priority Scrubbing
4.4. Performing Hierarchy Tagging
4.5. Programming Sensitivity Map Header File into Memory
4.6. Performing Lookup for Sensitivity Map Header
4.7. Using the Fault Injection Debugger
4.8. Analyzing SEU Errors Using Signal Tap
4.9. Intel® Quartus® Prime Software SEU FIT Reports
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3.1. SDM ECC Error Message Bits
The SDM ECC error message bits store the error message when the Intel® Stratix® 10 device detects an SDM ECC error.
The SDM ECC error message contains information about the sector address and the type of error. You can retrieve the contents of the error message from the generic_sdm_data_out signal of the Advanced SEU Detection Intel® FPGA IP.
Name | Width | Bit | Description |
---|---|---|---|
Sector address (Most significant 32-bit word in generic_sdm_data_out signal) |
32 | 31:24 | Reserved |
23:16 | Address of sector with error | ||
15:8 | Reserved | ||
7:4 | Error type:
|
||
3:0 | Reserved | ||
Error data (Least significant 32-bit word in generic_sdm_data_out signal) |
32 | 31:29 | SDM ECC error type:
|
28 | Correction status:
|
||
27:12 | Reserved | ||
11:0 |
Specific SDM and Subsystem ECC error type 101 details:
Specific SDM and Subsystem ECC error type 110 details:
|
Note: For uncorrectable SDM ECC error, Intel® recommends that you reconfigure the Intel® Stratix® 10 device.