Visible to Intel only — GUID: dnk1505291441418
Ixiasoft
1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
4.1. Setting SEU_ERROR Pin
4.2. Intel® Quartus® Prime SEU Software Settings
4.3. Enabling Priority Scrubbing
4.4. Performing Hierarchy Tagging
4.5. Programming Sensitivity Map Header File into Memory
4.6. Performing Lookup for Sensitivity Map Header
4.7. Using the Fault Injection Debugger
4.8. Analyzing SEU Errors Using Signal Tap
4.9. Intel® Quartus® Prime Software SEU FIT Reports
Visible to Intel only — GUID: dnk1505291441418
Ixiasoft
1.1. SEU Mitigation Techniques for Intel® Stratix® 10 Devices
Intel® Stratix® 10 SEU mitigation features can benefit the system by:
- Ensuring the system functions properly all the time
- Preventing a system malfunction caused by an SEU event.
- Handling the SEU event if it is critical to the system.
Area | SEU Mitigation Approach |
---|---|
Error Detection and Correction | You can enable the error detection and correction (EDC) feature for detecting CRAM SEU events and automatic correction of CRAM contents. |
Memory block error correction code | Intel® Stratix® 10 designs M20K memory blocks with special layout techniques and Error Correction Code (ECC) to reduce SEU Failures in time (FIT) rate to almost zero. |
SEU Sensitivity processing | You can use sensitivity processing to identify if the SEU on a CRAM bit location is critical or not critical to the function of your compiled FPGA design bitstream file. |
Fault injection | You can use fault injection feature to validate the system response to the SEU event by changing the CRAM state to trigger an error. |
Hierarchical tagging | A complementary capability to sensitivity processing and fault injection for reporting SEU and constraining injection to specific portions of design logic. |
Triple Modular Redundancy (TMR) | You can implement TMR technique on critical logic such as state machines. |