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1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
4.1. Setting SEU_ERROR Pin
4.2. Intel® Quartus® Prime SEU Software Settings
4.3. Enabling Priority Scrubbing
4.4. Performing Hierarchy Tagging
4.5. Programming Sensitivity Map Header File into Memory
4.6. Performing Lookup for Sensitivity Map Header
4.7. Using the Fault Injection Debugger
4.8. Analyzing SEU Errors Using Signal Tap
4.9. Intel® Quartus® Prime Software SEU FIT Reports
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3.2. SDM ECC Error Signals Behavior
When the Intel® Stratix® 10 device detects an SDM ECC error, the generic_sdm_valid_out signal of the Advanced SEU Detection IP goes high for one clock cycle.
Always monitor the generic_sdm_valid_out signal. When the generic_sdm_valid_out signal goes high, retrieve the SDM ECC error message content from the generic_sdm_data_out signal of the Advanced SEU Detection IP.
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