Intel® Stratix® 10 SEU Mitigation User Guide

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ID 683602
Date 2/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 SEU Mitigation Overview 2. Intel® Stratix® 10 Mitigation Techniques for CRAM 3. Secure Device Manager ECC Error Detection 4. Intel® Stratix® 10 SEU Mitigation Implementation Guides 5. Advanced SEU Detection Intel® FPGA IP References 6. Intel® Stratix® 10 Fault Injection Debugger References 7. Intel® Stratix® 10 SEU Mitigation User Guide Archives 8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
1. Intel® Stratix® 10 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques for Intel® Stratix® 10 Devices 1.2. Configuration RAM 1.3. Memory Blocks Error Correction Code (ECC) Support 1.4. Secure Device Manager ECC Error 1.5. Triple-Module Redundancy 1.6. Failure Rates
2. Intel® Stratix® 10 Mitigation Techniques for CRAM x
2.1. CRAM Error Detection and Correction 2.2. Internal Scrubbing and Priority Scrubbing 2.3. SEU Sensitivity Processing 2.4. Designating the Sensitivity of the Design Hierarchy 2.5. Evaluating a System's Response to Functional Upsets
2.1. CRAM Error Detection and Correction x
2.1.1. Error Message Queue 2.1.2. SEU_ERROR Pin Behavior
2.2. Internal Scrubbing and Priority Scrubbing x
2.2.1. Internal Scrubbing 2.2.2. Priority Scrubbing
2.3. SEU Sensitivity Processing x
2.3.1. Advanced SEU Detection IP Core
2.3.1. Advanced SEU Detection IP Core x
2.3.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.3.1.2. On-Chip Lookup Sensitivity Processing 2.3.1.3. Off-Chip Lookup Sensitivity Processing 2.3.1.4. SMH Lookup
2.3.1.3. Off-Chip Lookup Sensitivity Processing x
2.3.1.3.1. Off-Chip Lookup Sensitivity Processing Operation Flow
2.3.1.4. SMH Lookup x
2.3.1.4.1. SMH Revision 4 File Format
2.4. Designating the Sensitivity of the Design Hierarchy x
2.4.1. Hierarchy Tagging
2.5. Evaluating a System's Response to Functional Upsets x
2.5.1. Intel® Quartus® Prime Fault Injection Debugger
3. Secure Device Manager ECC Error Detection x
3.1. SDM ECC Error Message Bits 3.2. SDM ECC Error Signals Behavior
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides x
4.1. Setting SEU_ERROR Pin 4.2. Intel® Quartus® Prime SEU Software Settings 4.3. Enabling Priority Scrubbing 4.4. Performing Hierarchy Tagging 4.5. Programming Sensitivity Map Header File into Memory 4.6. Performing Lookup for Sensitivity Map Header 4.7. Using the Fault Injection Debugger 4.8. Analyzing SEU Errors Using Signal Tap 4.9. Intel® Quartus® Prime Software SEU FIT Reports
4.7. Using the Fault Injection Debugger x
4.7.1. Enabling the Fault Injection Debugger 4.7.2. Launching and Setting Up the Fault Injection Debugger 4.7.3. Configuring Your Device and the Fault Injection Debugger 4.7.4. Constraining Regions for Fault Injection 4.7.5. Injecting Errors 4.7.6. Injecting Double Adjacent Errors
4.7.5. Injecting Errors x
4.7.5.1. Injecting Errors to a Random Location 4.7.5.2. Injecting Errors to a Specific Location
4.7.6. Injecting Double Adjacent Errors x
4.7.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.7.6.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.9. Intel® Quartus® Prime Software SEU FIT Reports x
4.9.1. Enabling the Projected SEU FIT by Component Usage Report 4.9.2. SEU FIT Parameters Report 4.9.3. Projected SEU FIT by Component Usage Report
4.9.3. Projected SEU FIT by Component Usage Report x
4.9.3.1. Component FIT Rates 4.9.3.2. Raw FIT 4.9.3.3. Utilized FIT 4.9.3.4. Mitigated FIT 4.9.3.5. Architectural Vulnerability Factor
4.9.3.3. Utilized FIT x
4.9.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 4.9.3.3.2. Considerations for Small Designs
5. Advanced SEU Detection Intel® FPGA IP References x
5.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.2. Advanced SEU Detection Intel® FPGA IP Ports
6. Intel® Stratix® 10 Fault Injection Debugger References x
6.1. Fault Injection Debugger Interface Parameters 6.2. Fault Injection Debugger Command-Line Interface
1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide

6.2. Fault Injection Debugger Command-Line Interface

You can run the Fault Injection Debugger at the command line with the quartus_fid executable, which is useful if you want to perform fault injection from a script.
Table 10.   Fault Injection Debugger Command-Line Interface Arguments for Intel® Stratix® 10 Devices
Long Argument Short Argument Description
list l Display all installed hardware.
cable c To select the cable number.
auto a For auto detect operation. You must select only one cable for this operation.
index i Option to specify the active device or devices to inject soft error.

Full syntax:

@<device_position>=<file_path>#<operation>

where:

  • device_position is the position of active device counting from nearest to TDI
  • file_path is the active device's programming file
  • operation is the operation you want to perform4
    • P—Program/Configure
    • I—Inject fault

Command example:

quartus_fid --cable=1 --index=@2=abc.sof#P
number n

Option to specify the number of soft errors to inject. If you do not specify the number of errors, the Fault Injection Debugger executes the interactive mode. In the interactive mode, you can select to inject fault, read EMR, scrub errors, or quit.

Note: You can inject up to four soft errors.

Command examples:

  • To inject two errors: 
    quartus_fid --cable=1 --index=@2=abd.sof --number=2
  • To execute interactive mode: 
    quartus_fid --cable=1 --index=@2=abc.sof
  • To inject double adjacent errors in interactive mode:
    quartus_fid --cable=1 --index=@2=abc.sof
F <sector_location> <frame_location> <bit_location> + <frame_location> <bit_location>
smh s Option to specify the sensitivity map header file.

Full syntax:

@<device_position>=<file_path>#<region_info>

where:

  • device_position is the position of active device counting from nearest to TDI
  • file_path is the active device's .smh file
  • region_info is the intended .smh region information with the following format: <targeted_regions><allow non critical><allow overlapping>
    • targeted_regions = binary representation of the regions
      • Region 1 = 1
      • Region 2 = 2
      • Region 3 = 4
      • Region 4 = 8
      • Region 1 and 2 = 3 (from 1 + 2)
      • Region 1 and 3 = 5 (from 1 + 4)
    • allow non critical—N = allow injecting to non-critical bit
    • allow overlapping—O = allow injecting to bits with overlapping regions

    Examples:

    • To inject region 1 or 3 only: region_info = 5
    • To inject region 2 or non-critical bit, region_info = 4N
    • To inject any bit that has region 4 or non-critical bit, the region_info = 8NO

Command examples:

  • To inject one error in region 2:
    quartus_fid --cable=1 --index=@2=abc.sof --number=1 --smh=@2=abc.smh#2
  • To execute interactive mode in a specific region:
    quartus_fid --cable=1 --index=@2=abc.sof --smh=@2=abc.smh#2
user u Option to specify the user specific fault.

Full syntax:

@<device_position>=<sector-frame-bit-pair ?>#1 <sector-frame-bit-pair ?>#2 ... <sector-frame-bit?>#n

where:

  • device_position is the position of active device counting from nearest to TDI
  • sector-frame-bit-pair is the frame bit and sector location where the error is injected.5

Command example:

quartus_fid --cable=1 --index=@2=abc.sof --number=1 --user="@2=0x003c 0x000d 0x0269"
lutram — Option for LUTRAM checking during error injection activities.

Command example:

quartus_fid --cable=1 --index=@2=abc.sof --number=8 --lutram
time t Option to specify the interval time between injections.
Related Information
4 If you do not specify any operation, the default operation is "inject fault".
5 The maximum pair of frame-bit depends on argument n.
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