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1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
4.1. Setting SEU_ERROR Pin
4.2. Intel® Quartus® Prime SEU Software Settings
4.3. Enabling Priority Scrubbing
4.4. Performing Hierarchy Tagging
4.5. Programming Sensitivity Map Header File into Memory
4.6. Performing Lookup for Sensitivity Map Header
4.7. Using the Fault Injection Debugger
4.8. Analyzing SEU Errors Using Signal Tap
4.9. Intel® Quartus® Prime Software SEU FIT Reports
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4.9.3.1. Component FIT Rates
The Projected SEU FIT by Component report shows FIT for the following components:
- SRAM embedded memory in embedded processors hard IP and M20K or M10K blocks
- CRAM used for LUT masks and routing configuration bits
- LABs in MLAB mode
- I/O configuration registers, which the FPGA implements differently than CRAM and design flipflops
- Standard flipflops the design uses in the address and data registers of M20K blocks, in DSP blocks, and in hard IP
- User flipflops the design implements in logic cells (ALMs or LEs)