Visible to Intel only — GUID: nik1409855433977
Ixiasoft
Visible to Intel only — GUID: nik1409855433977
Ixiasoft
5.2. Standard PCS in Low Latency Configuration
To provide a low latency datapath, the PCS includes only the phase compensation FIFO in phase compensation mode, and optionally, the byte serializer and byte deserializer blocks, as shown in the following figure. The transceiver channel interfaces with the FPGA fabric through the PCS.
The maximum supported data rate varies depending on the customization and is identical to the custom configuration except that the 8B/10B block is disabled