Visible to Intel only — GUID: nik1409773889962
Ixiasoft
Visible to Intel only — GUID: nik1409773889962
Ixiasoft
3.1.1. Embedded Reset Controller Signals
Signal Name | Signal | Description |
---|---|---|
phy_mgmt_clk | Control Input | Clock for the embedded reset controller. |
phy_mgmt_clk_reset | Control Input | A high-to-low transition of this asynchronous reset signal initiates the automatic reset sequence control. Hold this signal high to keep the reset signals asserted. |
tx_ready | Status Output | A continuous high on this signal indicates that the transmitter (TX) channel is out of reset and is ready for data transmission. This signal is synchronous to phy_mgmt_clk. |
rx_ready | Status Output | A continuous high on this signal indicates that the receiver (RX) channel is out of reset and is ready for data reception. This signal is synchronous to phy_mgmt_clk. |
reconfig_busy | Status Output | An output from the Transceiver Reconfiguration Controller block indicates the status of the dynamic reconfiguration controller. At the first mgmt_clk_clk clock cycle after power-up, reconfig_busy remains low. This signal is asserted from the second mgmt_clk_clk clock cycle to indicate that the calibration process is in progress . When the calibration process is completed, the reconfig_busy signal is deasserted. This signal is also routed to the embedded reset controller by the Quartus® II software by embedding the signal in the reconfig_to_xcvr bus between the PHY IP and the Transceiver Reconfiguration Controller. |
pll_locked | Status Output | This signal is asserted when the TX PLL achieves lock to the input reference clock. When this signal is asserted high, the embedded reset controller deasserts the tx_digitalreset signal. |
rx_is_lockedtodata | Status Output | This signal is an optional output status port. When asserted, this signal indicates that the CDR is locked to the RX data and the CDR has changed from lock-to-reference (LTR) to lock-to-data (LTD) mode. |
rx_is_lockedtoref | Status Output | This is an optional output status port. When asserted, this signal indicates that the CDR is locked to the reference clock. |
mgmt_clk_clk | Clock | Clock for the Transceiver Reconfiguration Controller. This clock must be stable before releasing mgmt_rst_reset. |
mgmt_rst_reset | Reset | Reset for the Transceiver Reconfiguration Controller |