Visible to Intel only — GUID: nik1409872467709
Ixiasoft
Visible to Intel only — GUID: nik1409872467709
Ixiasoft
4.1.3. PIPE Transceiver Channel Placement Guidelines
Configuration | Data Channel Placement | Minimum Channel Utilization | Default Logical Data Channel Number for Master |
---|---|---|---|
x1 |
Any channel |
2 (1 data channel, 1 clock channel) |
Data_channel[0] |
x2 |
2 contiguous channels |
3 (2 data channels, 1 clock channel) |
Data_channel[1] |
x4 |
4 contiguous channels |
5 (4 data channels, 1 clock channel) |
Data_channel[1] |
x8 |
8 contiguous channels |
9 (8 data channels, 1 clock channel) |
Data_channel[0] |
To override the default data channel number for the Master channel, do following:
- Assign the Master channel to the same bank of CMU PLL.
- Apply the following Quartus II QSF assignment:
set_parameter -name master_ch_number <logical_data_channel_number> -to <"test:pcie_i|altera_xcvr_pipe:test_inst|av_xcvr_pipe_nr:pipe_nr_inst| av_xcvr_pipe_native:transceiver_core">
set_parameter -name master_ch_number 4 -to <"test:pcie_i|altera_xcvr_pipe:test_inst|av_xcvr_pipe_nr:pipe_nr_inst| av_xcvr_pipe_native:transceiver_core”>
set_parameter -name dummy_ch_required 1 -to <"test:pcie_i|altera_xcvr_pipe:test_inst|av_xcvr_pipe_nr:pipe_nr_inst| av_xcvr_pipe_native:transceiver_core">
The following four figures show examples of channel placement for PIPE x1, x2, x4, and x8 configurations.