Arria® V Device Handbook: Volume 2: Transceivers

ID 683573
Date 5/29/2020
Public
Document Table of Contents

4.1.3. PIPE Transceiver Channel Placement Guidelines

Table 58.  PIPE Channel Placement for PCIe Gen1 Placement by the Quartus II software may vary with design, resulting in higher channel utilization.
Configuration Data Channel Placement Minimum Channel Utilization Default Logical Data Channel Number for Master

x1

Any channel

2 (1 data channel, 1 clock channel)

Data_channel[0]

x2

2 contiguous channels

3 (2 data channels, 1 clock channel)

Data_channel[1]

x4

4 contiguous channels

5 (4 data channels, 1 clock channel)

Data_channel[1]

x8

8 contiguous channels

9 (8 data channels, 1 clock channel)

Data_channel[0]

To override the default data channel number for the Master channel, do following:

  1. Assign the Master channel to the same bank of CMU PLL.
  2. Apply the following Quartus II QSF assignment:
    set_parameter -name master_ch_number <logical_data_channel_number> 
    -to <"test:pcie_i|altera_xcvr_pipe:test_inst|av_xcvr_pipe_nr:pipe_nr_inst|
    av_xcvr_pipe_native:transceiver_core">
To support PIPE placement identical to PCIe HIP x8, use following two Quartus II QSF assignments:
set_parameter -name master_ch_number 4 -to <"test:pcie_i|altera_xcvr_pipe:test_inst|av_xcvr_pipe_nr:pipe_nr_inst|
av_xcvr_pipe_native:transceiver_core”>
set_parameter -name dummy_ch_required 1 -to <"test:pcie_i|altera_xcvr_pipe:test_inst|av_xcvr_pipe_nr:pipe_nr_inst|
av_xcvr_pipe_native:transceiver_core">
Note: For more information about the hard IP implementation of PCIe and restrictions, refer to the “Transceiver Banks” section of the Transceiver Architecture in Arria V Devices chapter.

The following four figures show examples of channel placement for PIPE x1, x2, x4, and x8 configurations.

Figure 96. Example of PIPE x1 Channel PlacementChannels shaded in blue provide the high-speed serial clock. Channels shaded in gray are data channels. You can place the PIPE data channels in any available channel in the transceiver bank.


Figure 97. Example of PIPE x2 Channel Placement


Figure 98. Example of PIPE x4 Channel PlacementChannels shaded in blue provide the high-speed serial clock. Channels shaded in gray are data channels.


Figure 99. Example of PIPE x8 Channel PlacementChannels shaded in blue provide the high-speed serial clock. Channels shaded in gray are data channels.