Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 10/31/2022
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Document Table of Contents x
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines x
Definitions Understanding SSN Guidelines: Clock and Asynchronous Control Input Signal Guidelines: Data Input Pin Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package Guidelines: I/O Restriction Rules Guidelines: Placement Restrictions for 1.0 V I/O Pin Guidelines: Analog-to-Digital Converter I/O Restriction Guidelines: Voltage-Referenced I/O Standards Restriction Guidelines: Adhere to the LVDS I/O Restrictions Rules Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers Guidelines: External Memory Interface I/O Restrictions Guidelines: ADC Ground Plane Connection Guidelines: Board Design for ADC Reference Voltage Pin Guidelines: Board Design for Analog Input Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Guidelines: Clock and Asynchronous Control Input Signal x
Schmitt-Trigger Input Buffer
Guidelines: Placement Restrictions for 1.0 V I/O Pin x
Calculating the Total Inductance for 1.0 V Pin Placement
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Understanding SSN

SSN is defined as a noise voltage induced onto a single victim I/O pin on a device due to the switching behavior of other aggressor I/O pins on the device. SSN can be divided into two types of noise: voltage noise and timing noise.

In a sample system with three pins, two of the pins (A and C) are switching, while one pin (B) is quiet. If the pins are driven in isolation, the voltage waveforms at the output of the buffers appear without noise interference, as shown by the solid curves at the left of the figure. However, when pins A and C are switching simultaneously, the noise generated by the switching is injected onto other pins. This noise manifests itself as a voltage noise on pin B and timing noise on pins A and C.

Figure 1. System with Three PinsIn this figure, the dotted curves show the voltage noise on pin B and timing noise on pins A and C.


Voltage noise is measured as the change in voltage of a signal due to SSN. When a signal is QH, it is measured as the change in voltage toward 0 V. When a signal is QL, it is measured as the change in voltage toward VCC.

Voltage noise can be caused by SSOs under two worst-case conditions:

  • The victim pin is high and the aggressor pins (SSOs) are switching from low to high
  • The victim pin is low and the aggressor pins (SSOs) are switching from high to low
Figure 2. Quiet High Output Noise Estimation on Pin B


Figure 3. Quiet Low Input Noise Estimation for Pin D


SSN can occur in any system, but the induced noise does not always result in failures. Voltage functional errors are caused by SSN on quiet victim pins only when the voltage values on the quiet pins change by a large voltage that the logic listening to that signal reads a change in the logic value. For QH signals, a voltage functional error occurs when noise events cause the voltage to fall below VIH. Similarly, for QL signals, a voltage functional error occurs when noise events cause the voltage to rise above VIL. Because VIH and VIL of the Intel device are different for different I/O standards, and because signals have different quiet voltage values, the absolute amount of SSN, measured in volts, cannot be used to determine if a voltage failure occurs. Instead, to assess the level of impact by SSN, you can quantify the SSN in terms of the percentage of signal margin in Intel devices.

Figure 4. Reporting Noise Margins


The figure shows four noise events, two on QH signals and two on QL signals. The two noise events on the right-side of the figure consume 50 percent of the signal margin and do not cause voltage functional errors. However, the two noise events on the left side of the figure consume 100 percent of the signal margin, which can cause a voltage functional error.

Noise caused by aggressor signals is synchronously related to the victim pin outside of the sampling window of a receiver. This noise affects the switching time of a victim pin but is not considered an input threshold violation failure.

Figure 5. Synchronous Voltage Noise with No Functional Error


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