Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 10/31/2022
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Document Table of Contents x
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines x
Definitions Understanding SSN Guidelines: Clock and Asynchronous Control Input Signal Guidelines: Data Input Pin Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package Guidelines: I/O Restriction Rules Guidelines: Placement Restrictions for 1.0 V I/O Pin Guidelines: Analog-to-Digital Converter I/O Restriction Guidelines: Voltage-Referenced I/O Standards Restriction Guidelines: Adhere to the LVDS I/O Restrictions Rules Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers Guidelines: External Memory Interface I/O Restrictions Guidelines: ADC Ground Plane Connection Guidelines: Board Design for ADC Reference Voltage Pin Guidelines: Board Design for Analog Input Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Guidelines: Clock and Asynchronous Control Input Signal x
Schmitt-Trigger Input Buffer
Guidelines: Placement Restrictions for 1.0 V I/O Pin x
Calculating the Total Inductance for 1.0 V Pin Placement
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Guidelines: Data Input Pin

For data input signals, fast edge rates cause simultaneously switching input (SSI) noise problem on the wide data bus.

The noise margin is measured at the VIH or VIL instead of the signal edges.

Table 1.  Maximum Recommended Data Input Signal Edge Rate for Intel® MAX® 10 DevicesThis table lists the recommended maximum data input signal edge rate with regards to the percentage of I/O pins usage in an I/O bank.
Percentage of Simultaneous Switching Pins in I/O Bank Recommended Maximum Data Input Signal Edge Rate
50% to 100% 0.6 V/ns
25% to 49% 1.0 V/ns
0% to 24% 1.5 V/ns
Note: If an input pin has an adjacent pin that operates as a toggling output, the edge rate of the input signal to the input pin must be 1.5 V/ns or faster.

If the data input signal exceeds the recommended signal edge rate, you can apply similar approach as the clock input signal to improve the signal integrity.

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