Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 10/31/2022
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Document Table of Contents x
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines x
Definitions Understanding SSN Guidelines: Clock and Asynchronous Control Input Signal Guidelines: Data Input Pin Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package Guidelines: I/O Restriction Rules Guidelines: Placement Restrictions for 1.0 V I/O Pin Guidelines: Analog-to-Digital Converter I/O Restriction Guidelines: Voltage-Referenced I/O Standards Restriction Guidelines: Adhere to the LVDS I/O Restrictions Rules Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers Guidelines: External Memory Interface I/O Restrictions Guidelines: ADC Ground Plane Connection Guidelines: Board Design for ADC Reference Voltage Pin Guidelines: Board Design for Analog Input Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Guidelines: Clock and Asynchronous Control Input Signal x
Schmitt-Trigger Input Buffer
Guidelines: Placement Restrictions for 1.0 V I/O Pin x
Calculating the Total Inductance for 1.0 V Pin Placement
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Guidelines: Board Design for Analog Input

The crosstalk requirement for analog to digital signal is -100 dB up to 2 GHz. There must be no parallel routing between analog input signals and I/O traces, and between analog input signals and FPGA I/O signal traces.
  • The ADC presents a switch capacitor load to the driving circuit. Therefore, the total RC constant, including package, trace, and parasitic driver must be less than 42.4 ns. This consideration is to ensure that the input signal is fully settled during the sampling phase.
  • If you reduce the total sampling rate, you can calculate the required settling time as 0.45 ÷ FS > 10.62 × RC constant .
  • To gain more total RC margin, Intel recommends that you make the driver source impedance as low as possible:
    • For non-prescaler channel—less than 1 kΩ
    • For prescaler channel—less than 11 Ω
    Note: Not adhering to the source impedance recommendation may impact parameters such as total harmonic distortion (THD), signal-to-noise and distortion ratio (SINAD), differential non-linearity (DNL), and integral non-linearity (INL).

Trace Routing

  • If possible, route the switching I/O traces on different layers.
  • There is no specific requirement for input signal trace impedance. However, the DC resistance for the input trace must be as low as possible.
  • Route the analog input signal traces as adjacent as possible to REFGND if there is no REFGND plane.
  • Use REFGND as ground reference for the ADC input signal.
  • For prescaler-enabled input signal, set the ground reference to REFGND. Performance degrades if the ground reference of prescaler-enabled input signal is set to common ground (GND).

Input Low Pass Filter Selection

  • Intel recommends that you place a low pass filter to filter out high frequency noise being aliased back onto the input signal.
  • Place the low pass filter as close as possible to the analog input signals.
  • The cut off frequency depends on the analog input frequency. Intel recommends that the Fcutoff @ -3dB is at least two times the input frequency.
  • You can download the ADC input SPICE model for ADC front end board design simulation from the Intel website.
Table 12.  RC Constant and Filter Value

This table is an example of the method to quantify the RC constant and identify the RC filter value.

Total RC Constant = (RDRIVER + RBOARD + RPACKAGE + RFILTER) × (CDRIVER + CBOARD + CPACKAGE + CFILTER + CPIN)

Driver Board Package Pin Capacitance (pF) RC Filter Fcutoff @ -3dB (MHz) Total RC Constant (ns) Settling Time (ns)
R (Ω) C (pF) R (Ω) C (pF) R (Ω) C (pF) R (Ω) C (pF)
5 2 5 17 3 5 6 60 550 4.82 42.34 42.4
10 2 5 17 3 5 6 50 580 5.49 41.48 42.4
Figure 8. Passive Low Pass Filter Example


Figure 9. First Order Active Low Pass Filter ExampleThis figure is an example. You can design nth order active low pass filter.


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