Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Download PDF
ID 683572
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines x
Definitions Understanding SSN Guidelines: Clock and Asynchronous Control Input Signal Guidelines: Data Input Pin Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package Guidelines: I/O Restriction Rules Guidelines: Placement Restrictions for 1.0 V I/O Pin Guidelines: Analog-to-Digital Converter I/O Restriction Guidelines: Voltage-Referenced I/O Standards Restriction Guidelines: Adhere to the LVDS I/O Restrictions Rules Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers Guidelines: External Memory Interface I/O Restrictions Guidelines: ADC Ground Plane Connection Guidelines: Board Design for ADC Reference Voltage Pin Guidelines: Board Design for Analog Input Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Guidelines: Clock and Asynchronous Control Input Signal x
Schmitt-Trigger Input Buffer
Guidelines: Placement Restrictions for 1.0 V I/O Pin x
Calculating the Total Inductance for 1.0 V Pin Placement
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Guidelines: Placement Restrictions for 1.0 V I/O Pin

To minimize the impact of simultaneous switching noise (SSN) on the I/O pins, ensure that the total mutual inductance (Lm) of the I/O pins in usage surrounding the 1.0 V I/O does not exceed the guidelines in the following table.
Table 3.  Total Lm Guidelines for Pins Surrounding the 1.0 V Pin
I/O Standard of Surrounding Pins Locations Relative to 1.0 V Pin Total Lm of Surrounding Pins
1.0 V Within the same bank The total Lm of the surrounding pins in the bank must not exceed 7.41 nH.
In an adjacent bank The total Lm of the surrounding pins in the adjacent bank must not exceed 7.41 nH.
Within the same bank and in an adjacent bank The sum of the total Lm of the surrounding pins in both banks must not exceed 7.41 nH.
Other than 1.0 V In an adjacent bank The total Lm of the surrounding pins in the adjacent bank must not exceed 1 nH.

Example scenarios where the 1.0 V pin is in bank 3 and surrounding pins are in banks 3 and 4:

  • Bank 3 and 4 are both 1.0 V—total Lm of all surrounding pins in both banks must not exceed 7.41 nH.
  • Bank 3 is 1.0 V but bank 4 is 2.5 V—total Lm of surrounding pins in bank 3 must not exceed 7.41 nH and total Lm in bank 4 must not exceed 1 nH.

Section Content
Calculating the Total Inductance for 1.0 V Pin Placement

Related Information
Level Two Title