Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Download PDF
ID 683572
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines x
Definitions Understanding SSN Guidelines: Clock and Asynchronous Control Input Signal Guidelines: Data Input Pin Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package Guidelines: I/O Restriction Rules Guidelines: Placement Restrictions for 1.0 V I/O Pin Guidelines: Analog-to-Digital Converter I/O Restriction Guidelines: Voltage-Referenced I/O Standards Restriction Guidelines: Adhere to the LVDS I/O Restrictions Rules Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers Guidelines: External Memory Interface I/O Restrictions Guidelines: ADC Ground Plane Connection Guidelines: Board Design for ADC Reference Voltage Pin Guidelines: Board Design for Analog Input Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Guidelines: Clock and Asynchronous Control Input Signal x
Schmitt-Trigger Input Buffer
Guidelines: Placement Restrictions for 1.0 V I/O Pin x
Calculating the Total Inductance for 1.0 V Pin Placement
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Guidelines: Analog-to-Digital Converter I/O Restriction

These restrictions are applicable if you use the analog-to-digital converter (ADC) block.

The Intel® Quartus® Prime software uses physics-based rules to define the number of I/Os allowed in a particular bank based on the I/O's drive strength. These rules are based on noise calculation to analyze accurately the impact of I/O placement on the ADC performance.

The physics-based rules are available for the following devices starting from these Intel® Quartus® Prime software versions:

  • From Intel® Quartus® Prime version 14.1— Intel® MAX® 10 10M04, 10M08, 10M40, and 10M50 devices.
  • From Intel® Quartus® Prime version 15.0.1— Intel® MAX® 10 10M02, 10M16, and 10M25 devices.

Geometry-Based Rules for Design Estimation

Intel highly recommends that you use the following geometry-based rules to ensure ADC performance. These guidelines help you to estimate the resources available and prevent additional critical warning from versions of the Intel® Quartus® Prime software that implements the physics-based rules.

Table 6.  Geometry-Based I/O Restrictions Related to ADC UsageThis table lists the I/O restrictions by Intel® MAX® 10 device package if you use one of the following features in your design:
  • You use the dedicated analog input (ANAIN1 or ANAIN2) or any dual function ADC I/O pins as ADC channel inputs.
  • You use the built-in temperature sensing diode (TSD).
Package Restriction/Guideline
All Disable all JTAG operation during ADC sampling. The ADC signal-to-noise and distortion ratio (SINAD) is not guaranteed during JTAG operation.

M153

U169

U324

F256

F484

F672

  • Banks 1A and 1B—you cannot use GPIO pins in these banks.
  • Banks 2, 3, 4, 5, 6, and 7—you can use GPIO pins located in these banks.
  • Bank 8—you can use a percentage of the GPIO pins in this bank based on drive strength:
    • For an example listing the percentage of GPIO pins allowed in bank 8 for the F484 package, refer to Table 7 2.
    • Use low drive strength (8 mA and below) and differential I/O standards.
    • You can use static pins such as RESET or CONTROL.
Note: The GPIO pins in bank 8 are constrained by physics-based rules. The Intel® Quartus® Prime software issues a critical warning if the I/O settings violate any of the I/O physics-based rule. Table 7 only provides an example for your reference.

E144

  • Bank 1A, 1B, 2, and 8—you cannot use GPIO pins in these banks.
  • Banks 4 and 6—you can use GPIO pins located in these banks.
  • Banks 3, 5, and 7—you can use a percentage of the GPIO pins in this bank based on drive strength:
    • For the percentage of GPIO pins allowed, refer to Table 8.
    • Use low drive strength (8 mA and below) and differential I/O standards.
Note: The GPIO pins in banks 3, 5, and 7 are constrained by physics-based rules. The Intel® Quartus® Prime software issues a critical warning if the I/O settings violate any of the I/O physics-based rule. Table 8 only provides an example for your reference.
Table 7.  I/O Usage Restriction for Bank 8 in Intel® MAX® 10 F484 PackageThis table lists the percentage of I/O pins available in I/O bank 8 if you use the dedicated analog input (ANAIN1 or ANAIN2) or any dual function ADC I/O pins as ADC channel. Refer to Table 9 for the list of I/O standards in each group.
I/O Standards TX RX Total Availability (%)
Group 1 18 18 36 100
Group 2 16 16 32 89
Group 3 7 11 18 50
Group 4 5 7 12 33
Group 5 4 6 10 28
Group 6 4 4 8 22
Group 7 0 8 8 22
Table 8.  I/O Usage Restriction for Banks 3, 5, and 7 in Intel® MAX® 10 E144 Package This table lists the percentage of I/O pins available in banks 3, 5, and 7 if you use the dedicated analog input (ANAIN1 or ANAIN2) or any dual function ADC I/O pins as ADC channel inputs. Refer to Table 9 for the list of I/O standards in each group.
I/O Standards Bank 3 Bank 5 Bank 7 Device I/O Availability (%)
TX RX Availability (%) TX RX Availability (%) TX RX Availability (%)
Group 1 7 8 88 6 6 100 4 3 100 54
Group 2 7 8 88 6 6 100 4 3 100 54
Group 3 4 5 50 6 6 100 2 0 29 45
Group 4 3 4 39 5 5 83 0 0 0 39
Group 5 2 3 28 5 5 83 0 0 0 37
Group 6 1 2 17 5 5 83 0 0 0 35
Group 7 0 0 0 5 5 83 0 0 0 32
Table 9.  I/O Standards Groups Categorized According to Drive Strengths
I/O Standard Group I/O Standards Name and Drive Strength
Group 1
  • 1.8 V LVDS
  • 2.5 V LVDS
  • 2.5 V RSDS
  • BLVDS at 4 mA
  • SLVS at 4 mA
Group 2
  • BLVDS at 8 mA
  • SLVS at 8 mA
  • Sub-LVDS at 8 mA
  • 1.8 V, 1.5 V, and 1.2 V HSTL Class I at 8 mA
  • SSTL-15 at 34 Ω or 40 Ω
  • SSTL-135 at 34 Ω or 40 Ω
  • HSUL-12 at 34 Ω or 40 Ω
  • SSTL-2 Class I at 8 mA
  • SSTL-18 Class I at 8 mA
  • SSTL-15 Class I at 8 mA
  • 2.5 V and 1.8 V LVTTL at 4 mA
  • 2.5 V, 1.8 V, 1.5 V, and 1.2 V LVCMOS at 4 mA
  • 1.8 V LVTTL at 2 mA
  • 1.8 V, 1.5 V, and 1.2 V LVCMOS at 2 mA
Group 3
  • BLVDS at 12 mA
  • SLVS at 12 mA
  • Sub-LVDS at 12 mA
  • SSTL-2 Class I at 10 mA or 12 mA
  • SSTL-18 Class I at 10 mA or 12 mA
  • SSTL-15 Class I at 10 mA or 12 mA
  • 1.8 V, 1.5 V, and 1.2 V HSTL Class I at 10 mA or 12 mA
  • SSTL-2 at 50 Ω
  • SSTL-18 at 50 Ω
  • SSTL-15 at 50 Ω
  • 1.8 V, 1.5 V and 1.2 V HSTL at 50 Ω
  • HSUL-12 at 48 Ω
  • 2.5 V and 1.8 V LVTTL at 50 Ω
  • 2.5 V, 1.8 V, 1.5 V, and 1.2 V LVCMOS at 50 Ω
  • 1.8 V LVTTL at 6 mA or 8 mA
  • 1.8 V, 1.5 V, and 1.2 V LVCMOS at 6 mA or 8 mA
  • 1.0 V LVCMOS
  • 3.0 V LVTTL at 4 mA
  • 3.0 V LVCMOS at 4 mA
Group 4
  • SSTL-18 Class II at 12 mA
  • 3.0 V LVTTL at 50 Ω
  • 3.0 V LVCMOS at 50 Ω
  • 2.5 V LVTTL at 8 mA
  • 2.5 V LVCMOS at 8 mA
  • 1.8 V LVTTL at 10 mA or 12 mA
  • 1.8 V, 1.5 V, and 1.2 V LVCMOS at 10 mA or 12 mA
  • 3.3 V LVCMOS at 2 mA
Group 5
  • SSTL-2 Class II at 16 mA
  • SSTL-18 Class II at 16 mA
  • SSTL-15 Class II at 16 mA
  • 1.8 V and 1.5 V HSTL Class II at 16 mA
  • 1.2 V HSTL Class II at 14 mA
  • SSTL-18 at 25 Ω
  • SSTL-15 at 25 Ω
  • SSTL-2 at 25 Ω
  • 1.8 V, 1.5 V, and 1.2 V HSTL at 25 Ω
  • 2.5 V and 1.8 V LVTTL at 25 Ω
  • 2.5 V, 1.8 V, 1.5 V, and 1.2 LVCMOS at 25 Ω
  • 1.8 V LVTTL at 16 mA
  • 1.8 V and 1.5 V LVCMOS at 16 mA
  • 2.5 V LVCMOS at 12 mA
  • 2.5 V LVTTL at 12 mA
  • 3.0 V LVCMOS at 8 mA
  • 3.0 V LVTTL at 8 mA
  • 3.3 V LVTTL at 4 mA or 8 mA
Group 6
  • 2.5 V LVTTL at 16 mA
  • 2.5 V LVCMOS at 16 mA
  • 3.0 V LVTTL at 12 mA
  • 3.0 V LVCMOS at 12 mA
  • 3.0 V LVTTL at 25 Ω
  • 3.0 V LVCMOS at 25 Ω
Group 7
  • 3.0 V LVTTL at 16 mA
  • 3.0 V LVCMOS at 16 mA
2 For all device packages, the software displays a warning message if the number of GPIO pins in bank 8 is more than the allowed percentage.
Level Two Title