Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 10/31/2022
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Document Table of Contents x
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines x
Definitions Understanding SSN Guidelines: Clock and Asynchronous Control Input Signal Guidelines: Data Input Pin Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package Guidelines: I/O Restriction Rules Guidelines: Placement Restrictions for 1.0 V I/O Pin Guidelines: Analog-to-Digital Converter I/O Restriction Guidelines: Voltage-Referenced I/O Standards Restriction Guidelines: Adhere to the LVDS I/O Restrictions Rules Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers Guidelines: External Memory Interface I/O Restrictions Guidelines: ADC Ground Plane Connection Guidelines: Board Design for ADC Reference Voltage Pin Guidelines: Board Design for Analog Input Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Guidelines: Clock and Asynchronous Control Input Signal x
Schmitt-Trigger Input Buffer
Guidelines: Placement Restrictions for 1.0 V I/O Pin x
Calculating the Total Inductance for 1.0 V Pin Placement
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Guidelines: External Memory Interface I/O Restrictions

These I/O rules are applicable if you use external memory interfaces in your design.

Two GPIOs Adjacent to DQ Pin Is Disabled

This limitation is applicable to Intel® MAX® 10 10M16, 10M25, 10M40, and 10M50 devices, and only if you use DDR3 and LPDDR2 SDRAM memory standards.

Table 11.  DDR3 and LPDDR2 Memory Interface Widths and Device Packages Where Two GPIOs Adjacent to DQ Pins Are DisabledThis table lists the combination of Intel® MAX® 10 10M16, 10M25, 10M40, and 10M50 device packages, and DDR3 and LPDDR2 memory interface widths where you cannot use two GPIO pins that are adjacent to the DQ pins.
Device Package Memory Interface Width (DDR3 and LPPDR2 only)
F256 x8, x16
U324 x8, x16
F484 x8, x16, x24
F672 x8, x16, x24

Total I/O Utilization in Bank Must Be 75 Percent or Less in Some Devices

If you use DDR3 or LPDDR2 SDRAM memory interface standards, you can generally use a maximum of 75 percent of the total number of I/O pins available in a bank. This restriction differs from device to device. In some devices packages you can use all 100 percent of the I/Os. The Intel® Quartus® Prime software will output an error message if the I/O usage per bank of that device is affected by this rule.

If you use DDR2 memory interface standards, you can assign 25 percent of the I/O pins as input pins only.

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