Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 10/31/2022
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Document Table of Contents x
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines x
Definitions Understanding SSN Guidelines: Clock and Asynchronous Control Input Signal Guidelines: Data Input Pin Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package Guidelines: I/O Restriction Rules Guidelines: Placement Restrictions for 1.0 V I/O Pin Guidelines: Analog-to-Digital Converter I/O Restriction Guidelines: Voltage-Referenced I/O Standards Restriction Guidelines: Adhere to the LVDS I/O Restrictions Rules Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers Guidelines: External Memory Interface I/O Restrictions Guidelines: ADC Ground Plane Connection Guidelines: Board Design for ADC Reference Voltage Pin Guidelines: Board Design for Analog Input Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Guidelines: Clock and Asynchronous Control Input Signal x
Schmitt-Trigger Input Buffer
Guidelines: Placement Restrictions for 1.0 V I/O Pin x
Calculating the Total Inductance for 1.0 V Pin Placement Total Mutual Inductance Calculation
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Calculating the Total Inductance for 1.0 V Pin Placement

You can calculate the total inductance of the surrounding pins by using mutual inductance values in the max10-1v-mutual-coupling.zip file.
  1. Download the max10-1v-mutual-coupling.zip file and extract the relevant mutual inductance spreadsheet for your device.
  2. In the mutual inductance spreadsheet, identify the pins in use.
  3. Calculate the total mutual inductance of the pin and surrounding pins in use to ensure that the placement adheres to the 1.0 V pin placement guideline.
  4. If the total inductance is above the guideline restriction, update your design to use other I/O pins that contribute less mutual inductance.

Total Mutual Inductance Calculation

Table 4.  Total Mutual Inductance ExamplesThe examples in this table refer to Table 5.
Example Condition Type Example Result
Pin F5 is assigned with the 1 V I/O standard. The surrounding pins, F4, H3, and H4 are in the same I/O bank and are also assigned with the 1.0 V I/O standard. Intrabank, all 1.0 V Total Lm of F4, H3, and H4 does not exceed 7.4 nH. The placement does not violate the restriction.
Pin F5 is assigned with the 1 V I/O standard. The surrounding pins, F4, H3, and H4 are in an adjacent I/O bank and are assigned with the 1.0 V I/O standard. Interbank, all 1.0 V Total Lm of F4, H3, and H4 does not exceed 7.4 nH. The placement does not violate the restriction.
Pin F5 is assigned with the 1 V I/O standard. The surrounding pins, F4, H3, and H4 are in an adjacent I/O bank and are assigned with the 2.5 V I/O standard. Interbank, mixed voltages Total Lm of F4, H3, and H4 exceeds 1.0 nH. Update your design to use other I/O pins with smaller mutual inductance.
Table 5.  Example Mutual Inductance Values
Pin Name Mutual Coupling Pin Mutual Inductance (nH)
F5 F5 3.496 1
F5 F4 1.378
F5 H3 0.273
F5 J4 0.263
F5 K4 0.222
F5 E4 0.194
F5 F3 0.176
F5 H4 0.175
F5 E3 0.174
F5 G3 0.167
F5 G4 0.161
Related Information
1 Self inductance for pin F5. Omit this value from the Lm calculation.
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