Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

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ID 683572
Date 10/31/2022
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Document Table of Contents x
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines x
Definitions Understanding SSN Guidelines: Clock and Asynchronous Control Input Signal Guidelines: Data Input Pin Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package Guidelines: I/O Restriction Rules Guidelines: Placement Restrictions for 1.0 V I/O Pin Guidelines: Analog-to-Digital Converter I/O Restriction Guidelines: Voltage-Referenced I/O Standards Restriction Guidelines: Adhere to the LVDS I/O Restrictions Rules Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers Guidelines: External Memory Interface I/O Restrictions Guidelines: ADC Ground Plane Connection Guidelines: Board Design for ADC Reference Voltage Pin Guidelines: Board Design for Analog Input Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2 Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
Guidelines: Clock and Asynchronous Control Input Signal x
Schmitt-Trigger Input Buffer
Guidelines: Placement Restrictions for 1.0 V I/O Pin x
Calculating the Total Inductance for 1.0 V Pin Placement
Intel® MAX® 10 FPGA Signal Integrity Design Guidelines

Guidelines: I/O Restriction Rules

For different I/O standards and conditions, you must limit the number of I/O pins. This I/O restriction rule is applicable if you use LVDS transmitters or receivers. Apply this restriction if one or more LVDS I/O standards reside in the I/O bank.
Table 2.  Maximum Percentage of I/O Pins Allowed for Specific I/O Standards in an I/O BankThis table lists the maximum number of general purpose output pins recommended in a bank in terms of percentage to the total number of I/O pins available in an I/O bank if you use these combinations of I/O standards and conditions.
I/O Standard Condition Max Output Pins Per Bank (%)
2.5 V LVTTL/LVCMOS 16 mA current strength or 25 Ω OCT 25
12 mA current strength 30
8 mA current strength or 50 Ω OCT 45
4 mA current strength 65
2.5 V SSTL — 100
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