AN 711: Power Reduction Features in Intel® Arria® 10 Devices

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ID 683566
Date 5/27/2022
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Document Table of Contents
Document Table of Contents x
AN 711: Power Reduction Features in Intel® Arria® 10 Devices
AN 711: Power Reduction Features in Intel® Arria® 10 Devices x
Power Reduction and Performance Intel® Arria® 10 Power Reduction Techniques System Topology Options SmartVID Topologies SmartVID Power Savings Estimation VID Design for Intel® Arria® 10 FPGAs Document Revision History for AN 711: Power Reduction Features in Intel® Arria® 10 Devices
Intel® Arria® 10 Power Reduction Techniques x
SmartVID SmartVID General Configuration
System Topology Options x
Power Sense Lines
SmartVID Topologies x
SmartVID Controller IP Core Parallel Control System PMBus Control System Single-Wire Interface PWM Control System
Parallel Control System x
Intel® Quartus® Prime Parallel Control System Instantiation Parallel SmartVID Regulator Implementation Guidelines
PMBus Control System x
PMBus System Implementation PMBus Voltage Regulators PMBus VID Implementation Guidelines
Single-Wire Interface PWM Control System x
Single-Wire Interface PWM System Implementation
SmartVID Power Savings Estimation x
Enabling SmartVID in the Intel® Quartus® Prime Software
VID Design for Intel® Arria® 10 FPGAs x
Parallel VID PMBus SmartVID VID Design Guidelines
AN 711: Power Reduction Features in Intel® Arria® 10 Devices

SmartVID Controller IP Core

Note: To avoid problems during board bring-up and testing, do not read the fuse register during any reset sequence of the SmartVID soft controller. Doing so interrupts the normal operation of the JTAG chain of the device.

The vidctl_vid_code port is the VID output code, which represents the 6-bit VID code. This value is also stored in the control and status register (CSR) and can be accessed via the Avalon® Memory-Mapped interface.

When interfacing between the IP and your system, you should read the output when vidctl_vid_code_avail is asserted. This means that a new valid VID code is ready to be read. After the VID code is read, assert vidctl_vid_ack to let the SmartVID Controller IP Core know that the VID code is taken and a new value can be computed.

The first VID code output will be the default value, which is 0.9 V. How often the value will change depends on the temperature. If the temperature change causes the value to be updated, the VID code reduces to the targeted VID value with the decrement of VID_STEP per update. Likewise, it increases from the targeted VID value to 0.9 V with the increment of VID_STEP per update. VID code is only updated after you acknowledge that the current value is being read by asserting the vidctl_vid_ack input port.

For the SmartVID supported voltage range, refer to the Intel® Arria® 10 Device Datasheet.

There are many other ports on the SmartVID controller that need to be connected and used to configure the core. Please refer to the SmartVID Controller IP Core User Guide for more details.

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