AN 711: Power Reduction Features in Intel® Arria® 10 Devices

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ID 683566
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
AN 711: Power Reduction Features in Intel® Arria® 10 Devices
AN 711: Power Reduction Features in Intel® Arria® 10 Devices x
Power Reduction and Performance Intel® Arria® 10 Power Reduction Techniques System Topology Options SmartVID Topologies SmartVID Power Savings Estimation VID Design for Intel® Arria® 10 FPGAs Document Revision History for AN 711: Power Reduction Features in Intel® Arria® 10 Devices
Intel® Arria® 10 Power Reduction Techniques x
SmartVID SmartVID General Configuration
System Topology Options x
Power Sense Lines
SmartVID Topologies x
SmartVID Controller IP Core Parallel Control System PMBus Control System Single-Wire Interface PWM Control System
Parallel Control System x
Intel® Quartus® Prime Parallel Control System Instantiation Parallel SmartVID Regulator Implementation Guidelines
PMBus Control System x
PMBus System Implementation PMBus Voltage Regulators PMBus VID Implementation Guidelines
Single-Wire Interface PWM Control System x
Single-Wire Interface PWM System Implementation
SmartVID Power Savings Estimation x
Enabling SmartVID in the Intel® Quartus® Prime Software
VID Design for Intel® Arria® 10 FPGAs x
Parallel VID PMBus SmartVID VID Design Guidelines
AN 711: Power Reduction Features in Intel® Arria® 10 Devices

Power Sense Lines

Sense lines from the die power rail to the ball accurately account for the voltage drop in the package at high currents. The power supply uses the sense lines as the feedback reference to avoid having the wrong voltage level under load. You must use the power sense lines in this fashion when using the SmartVID features.

The power sense lines are dedicated pins on the FPGA. Refer to the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines for details.

Figure 3. Power Sense Lines with Single and Multiple Regulator Configurations
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