AN 711: Power Reduction Features in Intel® Arria® 10 Devices

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ID 683566
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
AN 711: Power Reduction Features in Intel® Arria® 10 Devices
AN 711: Power Reduction Features in Intel® Arria® 10 Devices x
Power Reduction and Performance Intel® Arria® 10 Power Reduction Techniques System Topology Options SmartVID Topologies SmartVID Power Savings Estimation VID Design for Intel® Arria® 10 FPGAs Document Revision History for AN 711: Power Reduction Features in Intel® Arria® 10 Devices
Intel® Arria® 10 Power Reduction Techniques x
SmartVID SmartVID General Configuration
System Topology Options x
Power Sense Lines
SmartVID Topologies x
SmartVID Controller IP Core Parallel Control System PMBus Control System Single-Wire Interface PWM Control System
Parallel Control System x
Intel® Quartus® Prime Parallel Control System Instantiation Parallel SmartVID Regulator Implementation Guidelines
PMBus Control System x
PMBus System Implementation PMBus Voltage Regulators PMBus VID Implementation Guidelines
Single-Wire Interface PWM Control System x
Single-Wire Interface PWM System Implementation
SmartVID Power Savings Estimation x
Enabling SmartVID in the Intel® Quartus® Prime Software
VID Design for Intel® Arria® 10 FPGAs x
Parallel VID PMBus SmartVID VID Design Guidelines
AN 711: Power Reduction Features in Intel® Arria® 10 Devices

Power Reduction and Performance

The Intel® Arria® 10 family operates at higher performance levels than prior generation 28-nm FPGAs. With 20-nm design rules, you can achieve significant power savings compared to 28-nm FPGAs. You can achieve even more power savings by applying additional power reduction techniques on the core voltage.

Figure 1. Power Consumption ComparisonPotential reduction in power compared to the lowest-power mid-range 28-nm generation FPGAs.

Smaller geometries and changes to the basic architecture provide the initial power savings of up to 15% over prior generation Arria® V devices. Any static power increases are offset by reductions in dynamic power for an overall total power reduction. You can achieve up to 40% additional power savings through static power binning, and by controlling the core voltage. You can control the core voltage through SmartVID.

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