AN 711: Power Reduction Features in Intel® Arria® 10 Devices

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ID 683566
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
AN 711: Power Reduction Features in Intel® Arria® 10 Devices
AN 711: Power Reduction Features in Intel® Arria® 10 Devices x
Power Reduction and Performance Intel® Arria® 10 Power Reduction Techniques System Topology Options SmartVID Topologies SmartVID Power Savings Estimation VID Design for Intel® Arria® 10 FPGAs Document Revision History for AN 711: Power Reduction Features in Intel® Arria® 10 Devices
Intel® Arria® 10 Power Reduction Techniques x
SmartVID SmartVID General Configuration
System Topology Options x
Power Sense Lines
SmartVID Topologies x
SmartVID Controller IP Core Parallel Control System PMBus Control System Single-Wire Interface PWM Control System
Parallel Control System x
Intel® Quartus® Prime Parallel Control System Instantiation Parallel SmartVID Regulator Implementation Guidelines
PMBus Control System x
PMBus System Implementation PMBus Voltage Regulators PMBus VID Implementation Guidelines
Single-Wire Interface PWM Control System x
Single-Wire Interface PWM System Implementation
SmartVID Power Savings Estimation x
Enabling SmartVID in the Intel® Quartus® Prime Software
VID Design for Intel® Arria® 10 FPGAs x
Parallel VID PMBus SmartVID VID Design Guidelines
AN 711: Power Reduction Features in Intel® Arria® 10 Devices

PMBus SmartVID

In PMBus SmartVID, the VRM is initially set to output a default voltage (0.9 V) required by the FPGA device at power-on. Once the FPGA device is successfully powered-on and configured, the FPGA uses PMBus to inform the VRM that a voltage change is requested. Based on the new configuration, the VRM re-adjusts (raises or lowers) its output voltage automatically to meet the new voltage required by the FPGA. In turn, the Intel® Arria® 10 device’s VCC core power can be reduced by the square of the voltage multiplied by the current.

Implementing this feature requires both hardware and software (IP) support. For the hardware portion, the selected VRM for the VCC core must support the PMBus interface and remote sensing.

Figure 16. PMBus SmartVID Block DiagramThis PMBus SmartVID implementation uses the a Digital PowerSoC with PMBus Interface to deliver VCC core current.
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