AN 711: Power Reduction Features in Intel® Arria® 10 Devices

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ID 683566
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
AN 711: Power Reduction Features in Intel® Arria® 10 Devices
AN 711: Power Reduction Features in Intel® Arria® 10 Devices x
Power Reduction and Performance Intel® Arria® 10 Power Reduction Techniques System Topology Options SmartVID Topologies SmartVID Power Savings Estimation VID Design for Intel® Arria® 10 FPGAs Document Revision History for AN 711: Power Reduction Features in Intel® Arria® 10 Devices
Intel® Arria® 10 Power Reduction Techniques x
SmartVID SmartVID General Configuration
System Topology Options x
Power Sense Lines
SmartVID Topologies x
SmartVID Controller IP Core Parallel Control System PMBus Control System Single-Wire Interface PWM Control System
Parallel Control System x
Intel® Quartus® Prime Parallel Control System Instantiation Parallel SmartVID Regulator Implementation Guidelines
PMBus Control System x
PMBus System Implementation PMBus Voltage Regulators PMBus VID Implementation Guidelines
Single-Wire Interface PWM Control System x
Single-Wire Interface PWM System Implementation
SmartVID Power Savings Estimation x
Enabling SmartVID in the Intel® Quartus® Prime Software
VID Design for Intel® Arria® 10 FPGAs x
Parallel VID PMBus SmartVID VID Design Guidelines
AN 711: Power Reduction Features in Intel® Arria® 10 Devices

Parallel Control System

Note: Currently, the parallel control system is being implemented on some Intel® FPGA development boards. Contact your sales and service representative for availability.
Figure 4. Parallel Control System

The parallel output configuration uses an on-FPGA VID soft controller and parallel voltage regulator controller system. Together they create a value necessary to drive the correct data to the voltage regulator. The regulator decodes the parallel data and adjusts the voltage level to the FPGA. At power up, the bias network,which consists of weak pull-up and pull-down resistors, establishes the code for the default VCC voltage for the FPGA. When the SmartVID Controller IP takes control and is done with initializations, it outputs the voltage code. It then enables the tri-state buffer, taking control of the VCC level. Intel recommends that the enable signal originate from a specific pin (RZQ_2A) on the FPGA. Refer to the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines for more information about pin assignments.


Section Content
Intel Quartus Prime Parallel Control System Instantiation
Parallel SmartVID Regulator Implementation Guidelines

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