AN 711: Power Reduction Features in Intel® Arria® 10 Devices

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ID 683566
Date 5/27/2022
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Document Table of Contents
Document Table of Contents x
AN 711: Power Reduction Features in Intel® Arria® 10 Devices
AN 711: Power Reduction Features in Intel® Arria® 10 Devices x
Power Reduction and Performance Intel® Arria® 10 Power Reduction Techniques System Topology Options SmartVID Topologies SmartVID Power Savings Estimation VID Design for Intel® Arria® 10 FPGAs Document Revision History for AN 711: Power Reduction Features in Intel® Arria® 10 Devices
Intel® Arria® 10 Power Reduction Techniques x
SmartVID SmartVID General Configuration
System Topology Options x
Power Sense Lines
SmartVID Topologies x
SmartVID Controller IP Core Parallel Control System PMBus Control System Single-Wire Interface PWM Control System
Parallel Control System x
Intel® Quartus® Prime Parallel Control System Instantiation Parallel SmartVID Regulator Implementation Guidelines
PMBus Control System x
PMBus System Implementation PMBus Voltage Regulators PMBus VID Implementation Guidelines
Single-Wire Interface PWM Control System x
Single-Wire Interface PWM System Implementation
SmartVID Power Savings Estimation x
Enabling SmartVID in the Intel® Quartus® Prime Software
VID Design for Intel® Arria® 10 FPGAs x
Parallel VID PMBus SmartVID VID Design Guidelines
AN 711: Power Reduction Features in Intel® Arria® 10 Devices

PMBus VID Implementation Guidelines

PMBus VID implementation with Intel® Arria® 10 devices requires the following characteristics:
  • The regulator must support a default boot voltage prior to the issuing any VID commands.
  • The regulator must support PMBus logic voltages no higher than 1.8 V (nominal). If the regulator logic levels are greater than 1.8 V, then some form of voltage level shifter is required for at least SCL and SDA signals.
  • The regulator must support the PMBus Slave role with clock rates up to 400 kHz.
  • The regulator must support the PMBus VOUT_MODE(0x20, R) command. The PMBus Master uses the VOUT_MODE command to interrogate the regulator to discover the data format for the VOUT_COMMAND values. The PMBus Master can be the FPGA or a system power manager.
  • The regulator must support the PMBus VOUT_COMMAND (0x21, R/W) command. The PMBus Master uses the VOUT_COMMAND instruction in the data format retrieved from VOUT_MODE to write VID values to the regulator. The PMBus Master can be the FPGA or a system power manager. The VID voltage will change by no more than 10 mV per step.
  • If you require multiple parallel regulators to achieve the output current target, then the group of regulators must behave as a single regulator with respect to the VID functions. This implies having distinct addresses for each of the regulators, and for the regulators to respond to VOUT_COMMAND using the SMBus Group Command Protocol. The SMBus Group Command Protocol writes to each address using repeated starts, with all devices simultaneously executing the command on the last STOP symbol.
  • The regulator must accept a VID update rate of 10 ms, and the voltage must reach within the ±30 mV tolerance envelope within 10 ms of the last STOP symbol for transmitting VOUT_COMMAND. Voltage change for 10 mv should be between 20 µs and 45 µs for each step.
  • The regulator(s) must meet the static and ripple and dynamic power tolerances listed in the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines during all phases of power delivery after the boot voltage is reached.
Figure 9. Boot Sequence for Intel® Arria® 10 Devices Using PMBus SmartVID
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