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1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2.4.5.1. ebfm_barwr Procedure
2.4.5.2. ebfm_barwr_imm Procedure
2.4.5.3. ebfm_barrd_wait Procedure
2.4.5.4. ebfm_barrd_nowt Procedure
2.4.5.5. ebfm_cfgwr_imm_wait Procedure
2.4.5.6. ebfm_cfgwr_imm_nowt Procedure
2.4.5.7. ebfm_cfgrd_wait Procedure
2.4.5.8. ebfm_cfgrd_nowt Procedure
2.4.5.9. BFM Configuration Procedures
2.4.5.10. BFM Shared Memory Access Procedures
2.4.5.11. BFM Log and Message Procedures
2.4.5.12. Verilog HDL Formatting Functions
2.4.5.11.1. ebfm_display Verilog HDL Function
2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function
2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task
2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
2.4.5.11.5. ebfm_log_open Verilog HDL Function
2.4.5.11.6. ebfm_log_close Verilog HDL Function
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2.3.2.1. Testbench Modules
The top-level of the testbench instantiates the following main modules:
- altpcietb_bfm_rp_gen5x16.sv —This is the Root Port PCIe* BFM.
//Directory path <project_dir>/intel_rtile_pcie_ast_0_example_design/pcie_ed_tb/ip/pcie_ed_tb/dut_pcie_tb_ip/intel_rtile_pcie_tbed_<ver>/sim
- pcie_ed_dut.ip: This is the Endpoint design with the parameters that you specify.
//Directory path <project_dir>/intel_rtile_pcie_ast_0_example_design/ip/pcie_ed
- pcie_ed_pio0.ip: This module is a target and initiator of transactions for the PIO design example.
//Directory path <project_dir>/intel_rtile_pcie_ast_0_example_design/ip/pcie_ed
- pcie_ed_sriov0.ip: This module is a target and initiator of transactions for the SR-IOV design example.
//Directory path <project_dir>/intel_rtile_pcie_ast_0_example_design/ip/pcie_ed
In addition, the testbench has routines that perform the following tasks:
- Generates the reference clock for the Endpoint at the required frequency.
- Provides a PCI Express reset at start up.