R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.1.1.1. Credit Value Initialization and Return

The following table shows an example of a posted 1024-bit write sequence consuming one posted header credit and eight posted data credits.

Table 3.  Example of a 1024-bit Posted Write Sequence
Header               H0
Data D7 D6 D5 D4 D3 D2 D1 D0

A non-posted read sequence consumes one non-posted header credit only as shown in the table below.

Table 4.  Example of a Non-Posted Read Sequence
Header H0
Data