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1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2.4.5.1. ebfm_barwr Procedure
2.4.5.2. ebfm_barwr_imm Procedure
2.4.5.3. ebfm_barrd_wait Procedure
2.4.5.4. ebfm_barrd_nowt Procedure
2.4.5.5. ebfm_cfgwr_imm_wait Procedure
2.4.5.6. ebfm_cfgwr_imm_nowt Procedure
2.4.5.7. ebfm_cfgrd_wait Procedure
2.4.5.8. ebfm_cfgrd_nowt Procedure
2.4.5.9. BFM Configuration Procedures
2.4.5.10. BFM Shared Memory Access Procedures
2.4.5.11. BFM Log and Message Procedures
2.4.5.12. Verilog HDL Formatting Functions
2.4.5.11.1. ebfm_display Verilog HDL Function
2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function
2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task
2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
2.4.5.11.5. ebfm_log_open Verilog HDL Function
2.4.5.11.6. ebfm_log_close Verilog HDL Function
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2.3.1.2. VCS* Simulator
Perform the following steps to execute the simulation via a command line:
- Change to the simulation working directory: cd <my_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs.
- Execute the following command: sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ -debug_access+all" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ed_tb" | tee simulation.log
Note: The command above is a single-line command.
A successful simulation includes the following message: "Simulation stopped due to successful completion!"
Perform the following steps to execute the simulation in interactive mode. Note that in case you have already generated a simv executable in non-interactive mode, you need to delete the simv file and simv.diadir directory.
- Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -kdb -debug_access+all
- Execute the following command: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ -debug_access+all" SKIP_SIM=1 TOP_LEVEL_NAME="pcie_ed_tb"
- Start the simulation in interactive mode: simv -gui &