ID
683544
Date
12/04/2023
Public
Visible to Intel only — GUID: apt1614194886911
Ixiasoft
1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2.4.5.1. ebfm_barwr Procedure
2.4.5.2. ebfm_barwr_imm Procedure
2.4.5.3. ebfm_barrd_wait Procedure
2.4.5.4. ebfm_barrd_nowt Procedure
2.4.5.5. ebfm_cfgwr_imm_wait Procedure
2.4.5.6. ebfm_cfgwr_imm_nowt Procedure
2.4.5.7. ebfm_cfgrd_wait Procedure
2.4.5.8. ebfm_cfgrd_nowt Procedure
2.4.5.9. BFM Configuration Procedures
2.4.5.10. BFM Shared Memory Access Procedures
2.4.5.11. BFM Log and Message Procedures
2.4.5.12. Verilog HDL Formatting Functions
2.4.5.11.1. ebfm_display Verilog HDL Function
2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function
2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task
2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
2.4.5.11.5. ebfm_log_open Verilog HDL Function
2.4.5.11.6. ebfm_log_close Verilog HDL Function
Visible to Intel only — GUID: apt1614194886911
Ixiasoft
1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
Updated for: |
---|
Intel® Quartus® Prime Design Suite 23.4 |
IP Version 11.1.0 |
The following table presents an overview of the design examples supported by the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express.
Design Example | Hard IP Mode | Simulators Supported | Development Kits Supported |
---|---|---|---|
PIO | Gen5 1x16 1024-bit Endpoint | VCS* , VCS* MX, Siemens* EDA QuestaSim* , Xcelium* 1
Note: Simulation support is not available for Gen3 and Gen4 in this release of Intel® Quartus® Prime.
|
Intel Agilex® 7 I-Series FPGA Development Kit ES 2 |
Gen4 1x16 1024-bit Endpoint | |||
Gen3 1x16 1024-bit Endpoint | |||
Gen5 2x8 512-bit Endpoint | |||
Gen4 2x8 512-bit Endpoint | |||
Gen3 2x8 512-bit Endpoint | |||
SR-IOV | Gen5 1x16 1024-bit Endpoint | VCS* , VCS* MX, Siemens* EDA QuestaSim* , Xcelium* 1 | Intel Agilex® 7 I-Series FPGA Development Kit ES 2 |
Performance | Gen5 1x16 1024-bit Endpoint | Simulation for the Gen5 1x16 1024-bit Performance design example is supported. Simulation is not supported for the Gen5 2x8 512-bit Performance design example. |
Intel Agilex® 7 I-Series FPGA Development Kit ES 2 |
Section Content
Functional Description for the Programmed Input/Output (PIO) Design Example
Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example
Functional Description for the Performance Design Example
Hardware and Software Requirements
1 Xcelium* simulator support is only available in devices with the following OPN numbers: AGIx027R29AxxxxR3, AGIx027R29AxxxxR2, AGIx027R29BxxxxR3, AGIx023R18AxxxxR0, AGIx041R29DxxxxR0, AGIx041R29DxxxxR1, AGMx039R47AxxR0. For more details on OPN decoding, refer to the Intel Agilex® 7 FPGAs and SoCs Device Overview
2 For more information, refer to the Intel Agilex® 7 I-Series FPGA Development Kit