R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Download PDF
ID 683544
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express 2. Quick Start Guide 3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express x
1.1. Functional Description for the Programmed Input/Output (PIO) Design Example 1.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.3. Functional Description for the Performance Design Example 1.4. Hardware and Software Requirements
1.1. Functional Description for the Programmed Input/Output (PIO) Design Example x
1.1.1. Credit Initialization Sequence
1.1.1. Credit Initialization Sequence x
1.1.1.1. Credit Value Initialization and Return 1.1.1.2. Credit Distribution
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Root Port BFM 2.5. Compiling the Design Example 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulations 2.3.2. Testbench
2.3.1. Steps to Run Simulations x
2.3.1.1. Siemens EDA QuestaSim* Simulator 2.3.1.2. VCS* Simulator 2.3.1.3. VCS* MX Simulator 2.3.1.4. Xcelium* Simulator
2.3.2. Testbench x
2.3.2.1. Testbench Modules 2.3.2.2. Test Driver Module 2.3.2.3. PIO Design Example Testbench 2.3.2.4. SR-IOV Design Example Testbench
2.4. Root Port BFM x
2.4.1. BFM Memory Map 2.4.2. Configuration Space Bus and Device Numbering 2.4.3. Configuration of Root Port and Endpoint 2.4.4. Issuing Read and Write Transactions to the Application Layer 2.4.5. BFM Procedures and Functions
2.4.5. BFM Procedures and Functions x
2.4.5.1. ebfm_barwr Procedure 2.4.5.2. ebfm_barwr_imm Procedure 2.4.5.3. ebfm_barrd_wait Procedure 2.4.5.4. ebfm_barrd_nowt Procedure 2.4.5.5. ebfm_cfgwr_imm_wait Procedure 2.4.5.6. ebfm_cfgwr_imm_nowt Procedure 2.4.5.7. ebfm_cfgrd_wait Procedure 2.4.5.8. ebfm_cfgrd_nowt Procedure 2.4.5.9. BFM Configuration Procedures 2.4.5.10. BFM Shared Memory Access Procedures 2.4.5.11. BFM Log and Message Procedures 2.4.5.12. Verilog HDL Formatting Functions
2.4.5.9. BFM Configuration Procedures x
2.4.5.9.1. ebfm_cfg_rp_ep Procedure 2.4.5.9.2. ebfm_cfg_decode_bar Procedure
2.4.5.10. BFM Shared Memory Access Procedures x
2.4.5.10.1. Shared Memory Constants 2.4.5.10.2. shmem_write Task 2.4.5.10.3. shmem_read Function 2.4.5.10.4. shmem_display Verilog HDL Function 2.4.5.10.5. shmem_fill Procedure 2.4.5.10.6. shmem_chk_ok Function
2.4.5.11. BFM Log and Message Procedures x
2.4.5.11.1. ebfm_display Verilog HDL Function 2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function 2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task 2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 2.4.5.11.5. ebfm_log_open Verilog HDL Function 2.4.5.11.6. ebfm_log_close Verilog HDL Function
2.4.5.12. Verilog HDL Formatting Functions x
2.4.5.12.1. himage1 2.4.5.12.2. himage2 2.4.5.12.3. himage4 2.4.5.12.4. himage8 2.4.5.12.5. himage16 2.4.5.12.6. dimage1 2.4.5.12.7. dimage2 2.4.5.12.8. dimage3 2.4.5.12.9. dimage4 2.4.5.12.10. dimage5 2.4.5.12.11. dimage6 2.4.5.12.12. dimage7
2.7. Running the Design Example x
2.7.1. Running the PIO Design Example 2.7.2. Running the SR-IOV Design Example 2.7.3. Running the Performance Design Example
1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.7.3. Running the Performance Design Example

  1. Navigate to ./software/user/example under the design example directory.
  2. Compile the design example application:

    $ sudo make

  3. Run the test:

    $ sudo ./intel_fpga_pcie_link_test

    You can run the Intel FPGA IP PCIe link test in manual or automatic mode. Choose from:
    • In automatic mode, the application automatically selects the device. The test selects the Intel PCIe device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
    • In manual mode, the test queries you for the bus, device, and function numbers and BAR.
  4. For the Intel Agilex® 7 Development Kit, you can determine the BDF by typing the following command:

    $ lspci -d 1172:

    Note: This step is required if you run the Performance design example 2x8, in order to get the BDF of the two ports.
  5. Here is a sample transcript for the selection between automatic and manual modes:
    # ./intel_fpga_pcie_link_test
*********************************************************
Intel FPGA PCIe Link Test
Version 2.0
0: Automatically select a device
1: Manually select a device
*********************************************************
  6. The Performance design example for the Intel FPGA IP R-Tile Avalon Streaming Hard IP for PCI Express IP core only supports menu option 9. Enter 9 and press Enter to proceed.
    Opened a handle to BAR 0 of a device with BDF 0x3800
*********************************************************
 0: Link test - 100 writes and reads
 1: Write memory space
 2: Read memory space
 3: Write configuration space
 4: Read configuration space
 5: Change BAR for PIO
 6: Change device
 7: Enable SRIOV
 8: Do a link test for every enabled virtual function
    belonging to the current device
 9: Perform DMA for Throughput
10: Quit program
*********************************************************
> 9
  7. Select the R-Tile PCIe Hard IP mode.

  8. In case you select the 2x8 mode, the following menu is displayed, where you need to insert the BDF of each port, previously obtained in Step 4.

  9. Both modes allow you to run the Max Performance Test or Custom Performance Test.

  10. The option 0: Run Max Performance Test generates Memory Write traffic, Memory Read traffic and simultaneous Memory Write and Memory Read Traffic with the payload size and read request size that allow you to obtain the maximum performance.
    • Example of running Max Performance Test in the R-Tile PCIe Hard IP mode 1x16: 
      ********************************************************************
                MAX END POINT (EP) TRAFFIC
********************************************************************

   EXECUTING WRITE TRAFFIC...
100% [||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||]
   PERF WRITE GB/s: 59.9366

   EXECUTING READ TRAFFIC...
100% [||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||]
   PERF READ GB/s: 59.0977
    • Example of running Max Performance Test in the R-Tile PCIe Hard IP mode 2x8: 
      ********************************************************************
                MAX END POINT (EP) TRAFFIC
********************************************************************

   EXECUTING WRITE TRAFFIC...
100% [||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||]
   Device with BDF 0x3800. PERF WRITE GB/s: 29.95

   Device with BDF 0x3900. PERF WRITE GB/s: 29.95

   EXECUTING READ TRAFFIC...
100% [||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||]
   Device with BDF 0x3800. PERF READ GB/s: 29.19

   Device with BDF 0x3900. PERF READ GB/s: 29.28
  11. The option 1: Run Custom Performance Test allows you to configure the traffic sent during the performance test. By selecting this option, you will be able to enter the number of iterations to be carried out, the Payload size for Memory transactions, the Read Request Size for Memory Read transactions, as well as the type of traffic to execute. In case you select the 2x8 mode, the settings for each port will be required. If the numbers of loops differ between ports, the value provided in the second port will be taken.
Level Two Title