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1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2.4.5.1. ebfm_barwr Procedure
2.4.5.2. ebfm_barwr_imm Procedure
2.4.5.3. ebfm_barrd_wait Procedure
2.4.5.4. ebfm_barrd_nowt Procedure
2.4.5.5. ebfm_cfgwr_imm_wait Procedure
2.4.5.6. ebfm_cfgwr_imm_nowt Procedure
2.4.5.7. ebfm_cfgrd_wait Procedure
2.4.5.8. ebfm_cfgrd_nowt Procedure
2.4.5.9. BFM Configuration Procedures
2.4.5.10. BFM Shared Memory Access Procedures
2.4.5.11. BFM Log and Message Procedures
2.4.5.12. Verilog HDL Formatting Functions
2.4.5.11.1. ebfm_display Verilog HDL Function
2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function
2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task
2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
2.4.5.11.5. ebfm_log_open Verilog HDL Function
2.4.5.11.6. ebfm_log_close Verilog HDL Function
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2.4.5.10.2. shmem_write Task
The shmem_write procedure writes data to the BFM shared memory.
Location |
altpcietb_g3bfm_shmem.v |
|
---|---|---|
Syntax |
shmem_write(addr, data, leng) |
|
Arguments |
addr | BFM shared memory starting address for writing data |
data | Data to write to BFM shared memory. This parameter is implemented as a 64‑bit vector. leng is 1–8 bytes. Bits 7 down to 0 are written to the location specified by addr; bits 15 down to 8 are written to the addr+1 location, etc. |
|
length | Length, in bytes, of data written |