Stratix® 10 General Purpose I/O User Guide

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ID 683518
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 I/O Overview 2. Stratix® 10 I/O Architecture and Features 3. Stratix® 10 I/O Design Considerations 4. Stratix® 10 I/O Implementation Guides 5. GPIO Intel® FPGA IP Reference 6. Document Revision History for the Stratix® 10 General Purpose I/O User Guide
1. Stratix® 10 I/O Overview x
1.1. Stratix® 10 I/O and Differential I/O Buffers 1.2. Stratix® 10 I/O Migration Support
2. Stratix® 10 I/O Architecture and Features x
2.1. I/O Standards and Voltage Levels in Stratix® 10 Devices 2.2. I/O Element Structure in Stratix® 10 Devices 2.3. Programmable IOE Features in Stratix® 10 Devices 2.4. On-Chip I/O Termination in Stratix® 10 Devices 2.5. External I/O Termination for Stratix® 10 Devices
2.1. I/O Standards and Voltage Levels in Stratix® 10 Devices x
2.1.1. Stratix® 10 I/O Standards Support 2.1.2. Stratix® 10 I/O Standards Voltage Support
2.2. I/O Element Structure in Stratix® 10 Devices x
2.2.1. I/O Bank Architecture in Stratix® 10 Devices 2.2.2. I/O Buffer and Registers in Stratix® 10 Devices
2.3. Programmable IOE Features in Stratix® 10 Devices x
2.3.1. Programmable Output Slew Rate Control 2.3.2. Programmable IOE Delay 2.3.3. Programmable Open-Drain Output 2.3.4. Programmable Bus Hold 2.3.5. Programmable Pull-Up Resistor 2.3.6. Programmable Pre-Emphasis 2.3.7. Programmable Differential Output Voltage 2.3.8. Programmable Current Strength
2.4. On-Chip I/O Termination in Stratix® 10 Devices x
2.4.1. RS OCT without Calibration in Stratix® 10 Devices 2.4.2. RS OCT with Calibration in Stratix® 10 Devices 2.4.3. RT OCT with Calibration in Stratix® 10 Devices 2.4.4. Dynamic OCT 2.4.5. Differential Input RD OCT 2.4.6. OCT Calibration Block in Stratix® 10 Devices
2.5. External I/O Termination for Stratix® 10 Devices x
2.5.1. Single-Ended I/O Termination 2.5.2. Differential I/O Termination for Stratix® 10 Devices
2.5.2. Differential I/O Termination for Stratix® 10 Devices x
2.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination 2.5.2.2. LVDS, RSDS, and Mini-LVDS Termination 2.5.2.3. LVPECL Termination
3. Stratix® 10 I/O Design Considerations x
3.1. Guideline: VREF Sources and VREF Pins 3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards 3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing 3.5. Guideline: Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down 3.6. Guideline: Maximum DC Current Restrictions 3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks 3.8. Guideline: I/O Standards Limitation for Stratix® 10 TX 400 3.9. Guideline: I/O Standards Limitation for Stratix® 10 GX 400 and SX 400
4. Stratix® 10 I/O Implementation Guides x
4.1. GPIO Intel® FPGA IP 4.2. Verifying Resource Utilization and Design Performance 4.3. GPIO Intel® FPGA IP Timing 4.4. GPIO Intel® FPGA IP Design Examples 4.5. Verifying Pin Migration Compatibility 4.6. IP Migration to the GPIO IP Core
4.1. GPIO Intel® FPGA IP x
4.1.1. Release Information for GPIO Intel® FPGA IP 4.1.2. GPIO Intel® FPGA IP Data Paths 4.1.3. Register Packing
4.1.2. GPIO Intel® FPGA IP Data Paths x
4.1.2.1. Input Path 4.1.2.2. Output and Output Enable Paths
4.3. GPIO Intel® FPGA IP Timing x
4.3.1. Timing Components 4.3.2. Delay Elements 4.3.3. Timing Analysis 4.3.4. Timing Closure Guidelines
4.3.3. Timing Analysis x
4.3.3.1. Single Data Rate Input Register 4.3.3.2. Full-Rate or Half-Rate DDIO Input Register 4.3.3.3. Single Data Rate Output Register 4.3.3.4. Full-Rate or Half-Rate DDIO Output Register
4.4. GPIO Intel® FPGA IP Design Examples x
4.4.1. GPIO Intel® FPGA IP Synthesizable Quartus® Prime Design Example 4.4.2. GPIO Intel® FPGA IP Simulation Design Example
4.6. IP Migration to the GPIO IP Core x
4.6.1. Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores 4.6.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
5. GPIO Intel® FPGA IP Reference x
5.1. GPIO Intel® FPGA IP Parameter Settings 5.2. GPIO Intel® FPGA IP Interface Signals
5.2. GPIO Intel® FPGA IP Interface Signals x
5.2.1. Shared Signals 5.2.2. Data Bit-Order for Data Interface 5.2.3. Data Interface Signals and Corresponding Clocks
1. Stratix® 10 I/O Overview
2. Stratix® 10 I/O Architecture and Features
3. Stratix® 10 I/O Design Considerations
4. Stratix® 10 I/O Implementation Guides
5. GPIO Intel® FPGA IP Reference
6. Document Revision History for the Stratix® 10 General Purpose I/O User Guide

1.1. Stratix® 10 I/O and Differential I/O Buffers

The general purpose I/Os (GPIOs) consist of the following I/O banks:

  • LVDS I/O bank—supports differential and single-ended I/O standards up to 1.8 V. The LVDS I/O pins form pairs of true differential LVDS channels. Each pair supports a parallel input/output termination between the two pins. You can use each LVDS channel as transmitter only or receiver only. Each LVDS channel supports transmit SERDES and receive SERDES with DPA circuitry. For example, if you use 30 channels of the available 72 channels as transmitters, you can use the remaining 42 channels as receivers.
  • 3 V I/O bank—supports single-ended LVCMOS and LVTTL I/O standards up to 3.0 V. In Stratix® 10 devices, each 3 V I/O bank supports only two output enables (OE) for its eight single-ended I/Os. Single-ended I/Os within this I/O bank support all programmable I/O element (IOE) features except:
    • Programmable pre-emphasis
    • RD on-chip termination (OCT)
    • Calibrated RS and RT OCT
    • Internal VREF generation
    • Dynamic OCT
  • 3.3 V I/O bank—supports single-ended LVCMOS and LVTTL I/O standards at 3.3 V and 3.0 V. This feature is available only in the HF35 package of the Stratix® 10 GX 400 and SX 400 devices. The 3.3 V I/O buffer is unidirectional. You can configure the I/O pins in the bank in preset groups of eight pins—as all input pins or all output pins. The bank supports the following features:
    • As input—programmable pull up resistor
    • As output—programmable current strength
Note: The 3 V I/O banks in Stratix® 10 devices do not support the DDIO feature of the GPIO IP core. Bypass the DDIO if you use an I/O standard supported only by 3 V I/O banks, such as 3.0 V LVCMOS. To bypass the DDIO feature, set the Register mode of the GPIO IP core to none.
Note: The 3 V I/O banks are located on the Stratix® 10 transceiver tiles. These banks are available only on the L-Tile and H-Tile transceiver tiles.
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