Stratix® 10 General Purpose I/O User Guide

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ID 683518
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 I/O Overview 2. Stratix® 10 I/O Architecture and Features 3. Stratix® 10 I/O Design Considerations 4. Stratix® 10 I/O Implementation Guides 5. GPIO Intel® FPGA IP Reference 6. Document Revision History for the Stratix® 10 General Purpose I/O User Guide
1. Stratix® 10 I/O Overview x
1.1. Stratix® 10 I/O and Differential I/O Buffers 1.2. Stratix® 10 I/O Migration Support
2. Stratix® 10 I/O Architecture and Features x
2.1. I/O Standards and Voltage Levels in Stratix® 10 Devices 2.2. I/O Element Structure in Stratix® 10 Devices 2.3. Programmable IOE Features in Stratix® 10 Devices 2.4. On-Chip I/O Termination in Stratix® 10 Devices 2.5. External I/O Termination for Stratix® 10 Devices
2.1. I/O Standards and Voltage Levels in Stratix® 10 Devices x
2.1.1. Stratix® 10 I/O Standards Support 2.1.2. Stratix® 10 I/O Standards Voltage Support
2.2. I/O Element Structure in Stratix® 10 Devices x
2.2.1. I/O Bank Architecture in Stratix® 10 Devices 2.2.2. I/O Buffer and Registers in Stratix® 10 Devices
2.3. Programmable IOE Features in Stratix® 10 Devices x
2.3.1. Programmable Output Slew Rate Control 2.3.2. Programmable IOE Delay 2.3.3. Programmable Open-Drain Output 2.3.4. Programmable Bus Hold 2.3.5. Programmable Pull-Up Resistor 2.3.6. Programmable Pre-Emphasis 2.3.7. Programmable Differential Output Voltage 2.3.8. Programmable Current Strength
2.4. On-Chip I/O Termination in Stratix® 10 Devices x
2.4.1. RS OCT without Calibration in Stratix® 10 Devices 2.4.2. RS OCT with Calibration in Stratix® 10 Devices 2.4.3. RT OCT with Calibration in Stratix® 10 Devices 2.4.4. Dynamic OCT 2.4.5. Differential Input RD OCT 2.4.6. OCT Calibration Block in Stratix® 10 Devices
2.5. External I/O Termination for Stratix® 10 Devices x
2.5.1. Single-Ended I/O Termination 2.5.2. Differential I/O Termination for Stratix® 10 Devices
2.5.2. Differential I/O Termination for Stratix® 10 Devices x
2.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination 2.5.2.2. LVDS, RSDS, and Mini-LVDS Termination 2.5.2.3. LVPECL Termination
3. Stratix® 10 I/O Design Considerations x
3.1. Guideline: VREF Sources and VREF Pins 3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards 3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing 3.5. Guideline: Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down 3.6. Guideline: Maximum DC Current Restrictions 3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks 3.8. Guideline: I/O Standards Limitation for Stratix® 10 TX 400 3.9. Guideline: I/O Standards Limitation for Stratix® 10 GX 400 and SX 400
4. Stratix® 10 I/O Implementation Guides x
4.1. GPIO Intel® FPGA IP 4.2. Verifying Resource Utilization and Design Performance 4.3. GPIO Intel® FPGA IP Timing 4.4. GPIO Intel® FPGA IP Design Examples 4.5. Verifying Pin Migration Compatibility 4.6. IP Migration to the GPIO IP Core
4.1. GPIO Intel® FPGA IP x
4.1.1. Release Information for GPIO Intel® FPGA IP 4.1.2. GPIO Intel® FPGA IP Data Paths 4.1.3. Register Packing
4.1.2. GPIO Intel® FPGA IP Data Paths x
4.1.2.1. Input Path 4.1.2.2. Output and Output Enable Paths
4.3. GPIO Intel® FPGA IP Timing x
4.3.1. Timing Components 4.3.2. Delay Elements 4.3.3. Timing Analysis 4.3.4. Timing Closure Guidelines
4.3.3. Timing Analysis x
4.3.3.1. Single Data Rate Input Register 4.3.3.2. Full-Rate or Half-Rate DDIO Input Register 4.3.3.3. Single Data Rate Output Register 4.3.3.4. Full-Rate or Half-Rate DDIO Output Register
4.4. GPIO Intel® FPGA IP Design Examples x
4.4.1. GPIO Intel® FPGA IP Synthesizable Quartus® Prime Design Example 4.4.2. GPIO Intel® FPGA IP Simulation Design Example
4.6. IP Migration to the GPIO IP Core x
4.6.1. Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores 4.6.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
5. GPIO Intel® FPGA IP Reference x
5.1. GPIO Intel® FPGA IP Parameter Settings 5.2. GPIO Intel® FPGA IP Interface Signals
5.2. GPIO Intel® FPGA IP Interface Signals x
5.2.1. Shared Signals 5.2.2. Data Bit-Order for Data Interface 5.2.3. Data Interface Signals and Corresponding Clocks
1. Stratix® 10 I/O Overview
2. Stratix® 10 I/O Architecture and Features
3. Stratix® 10 I/O Design Considerations
4. Stratix® 10 I/O Implementation Guides
5. GPIO Intel® FPGA IP Reference
6. Document Revision History for the Stratix® 10 General Purpose I/O User Guide

2.1.1. Stratix® 10 I/O Standards Support

Table 1.   Stratix® 10 Devices I/O Standards Support for FPGA I/O
I/O Standard I/O Buffer Type Support Application Standard Support
LVDS I/O 3 V I/O1 2 3.3 V I/O3
3.3 V LVTTL/3.3 V LVCMOS No No Yes General purpose JESD8-B
3.0 V LVTTL/3.0 V LVCMOS No Yes 4 Yes General purpose JESD8-B
2.5 V LVCMOS No Yes 5 No General purpose JESD8-5
1.8 V LVCMOS Yes Yes 5 No General purpose JESD8-7
1.5 V LVCMOS Yes Yes 5 No General purpose JESD8-11
1.2 V LVCMOS Yes Yes 5 No General purpose JESD8-12
SSTL-18 Class I and Class II Yes No No Flash interface JESD8-15
SSTL-15 Class I and Class II Yes No No DDR3 —
SSTL-15 Yes No No DDR3 JESD79-3D
SSTL-135 Yes No No DDR3L —
SSTL-125 6 Yes No No QDR-IV —
SSTL-12 Yes No No RLDRAM 3, QDR-IV —
POD12 Yes No No DDR4, QDR-IV JESD8-24
1.8 V HSTL Class I and Class II Yes No No DDR II+, QDR II+, and RLDRAM 2 JESD8-6
1.5 V HSTL Class I and Class II Yes No No DDR II+, QDR II+, QDR II, and RLDRAM 2 JESD8-6
1.2 V HSTL Class I and Class II Yes No No QDR-IV, General purpose JESD8-16A
HSUL-12 Yes No No LPDDR2, LPDDR3 —
Differential SSTL-18 Class I and Class II Yes No No General purpose JESD8-15
Differential SSTL-15 Class I and Class II Yes No No DDR3 —
Differential SSTL-15 Yes No No DDR3 JESD79-3D
Differential SSTL-135 Yes No No DDR3L —
Differential SSTL-1256 Yes No No General purpose —
Differential SSTL-12 Yes No No RLDRAM 3 —
Differential POD12 Yes No No DDR4 JESD8-24
Differential 1.8 V HSTL Class I and Class II Yes No No DDR II+, QDR II+, and RLDRAM 2 JESD8-6
Differential 1.5 V HSTL Class I and Class II Yes No No DDR II+, QDR II+, QDR II, and RLDRAM 2 JESD8-6
Differential 1.2 V HSTL Class I and Class II Yes No No General purpose JESD8-16A
Differential HSUL-12 Yes No No LPDDR2, LPDDR3 —
LVDS 7 Yes No No SGMII, SFI, SPI ANSI/TIA/EIA-644
Mini-LVDS 7 Yes No No SGMII, SFI, SPI —
RSDS7 Yes No No SGMII, SFI, SPI —
LVPECL Yes No No SGMII, SFI, SPI —
Note: To use the 1.2 V, 1.5 V, 1.8 V, 2.5, or 3.0 V I/O standards in the 3 V I/O bank, you must set the USE_AS_3V_GPIO assignment to the I/O pin. In the Quartus® Prime Settings File (.qsf), specify the following assignment: set_instance_assignment -name USE_AS_3V_GPIO ON -to <your pin name>
Table 2.   Stratix® 10 SX Devices I/O Standards Support for HPS I/O
I/O Standard Application Standard Support
1.8 V LVCMOS General purpose JESD8-7
1 Available only on L-Tile and H-Tile transceiver tiles.
2 When a transceiver tile is powered down, the tile's 3 V I/O bank is not available.
3 Available only on I/O bank 3C of the HF35 package of the Stratix® 10 GX 400 and SX 400 devices.
4 For the HF35 package of the Stratix® 10 GX 400 and SX 400 devices, the Quartus® Prime software automatically implements the 3 V I/O standard using I/O bank 3C. For H-Tile and L-Tile devices, you must set the USE_AS_3V_GPIO Quartus® Prime assignment to the pin.
5 You must set the USE_AS_3V_GPIO Quartus® Prime assignment to the pin.
6 Even though the Stratix® 10 I/O buffers support various I/O standards for memory application, Altera validates and support only IPs for memory interfaces listed in the External Memory Interfaces Stratix® 10 FPGA IP User Guide.
7 Supported only on dedicated clock pin in I/O banks 3A and 3D of the Stratix® 10 TX 400, GX 400, and SX 400 devices.
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