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Ixiasoft
2.1. I/O Planning Overview
2.2. Assigning I/O Pins
2.3. Importing and Exporting I/O Pin Assignments
2.4. Validating Pin Assignments
2.5. Verifying I/O Timing
2.6. Viewing Routing and Timing Delays
2.7. Analyzing Simultaneous Switching Noise
2.8. Scripting API
2.9. Managing Device I/O Pins Revision History
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Ixiasoft
1.1.2. Node, Entity, and Instance-Level Constraints
Node, entity, and instance-level constraints apply to a subset of the design hierarchy. These constraints take precedence over any global assignment that affects the same sections of the design hierarchy.
Assignment Type | Example | Assignment Editor | Chip Planner | Pin Planner |
---|---|---|---|---|
Pin | Project files | X | X | |
Location |
|
X | X | |
Routing |
|
X | X | |
Simulation | Vector input source | X | X | X |