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2.1. I/O Planning Overview
2.2. Assigning I/O Pins
2.3. Importing and Exporting I/O Pin Assignments
2.4. Validating Pin Assignments
2.5. Verifying I/O Timing
2.6. Viewing Routing and Timing Delays
2.7. Analyzing Simultaneous Switching Noise
2.8. Scripting API
2.9. Managing Device I/O Pins Revision History
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2.5.1.5. Advanced I/O Timing Analysis Reports
The following reports show advanced I/O timing analysis information:
I/O Timing Report | Description |
---|---|
Timing Analyzer Report | Reports signal integrity and board delay data. |
Board Trace Model Assignments report | Summarizes the board trace model component settings for each output and bidirectional signal. |
Signal Integrity Metrics report | Contains all the signal integrity metrics calculated during advanced I/O timing analysis based on the board trace model settings for each output or bidirectional pin. Includes measurements at both the FPGA pin and at the far-end load of board delay, steady state voltages, and rise and fall times. |
Note: By default, the Timing Analyzer generates the Slow‑Corner Signal Integrity Metrics report. To generate a Fast-Corner Signal Integrity Metrics report you must change the delay model by clicking Tools > Timing Analyzer.
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