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Ixiasoft
2.1. I/O Planning Overview
2.2. Assigning I/O Pins
2.3. Importing and Exporting I/O Pin Assignments
2.4. Validating Pin Assignments
2.5. Verifying I/O Timing
2.6. Viewing Routing and Timing Delays
2.7. Analyzing Simultaneous Switching Noise
2.8. Scripting API
2.9. Managing Device I/O Pins Revision History
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Ixiasoft
2.5.1. Running Advanced I/O Timing
Advanced I/O timing analysis uses your board trace model and termination network specification to report accurate output buffer-to-pin timing estimates, FPGA pin and board trace signal integrity and delay values. Advanced I/O timing runs automatically for supported devices during compilation.