Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

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ID 683492
Date 1/10/2019
Public
Document Table of Contents
Document Table of Contents x
1. Constraining Designs 2. Managing Device I/O Pins A. Intel® Quartus® Prime Standard Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints Designs in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints Designs in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Intel® Quartus® Prime GUI 1.1.4. Specifying Timing Constraints in the GUI
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify I/O Constraints in Pin Planner 1.1.2.3. Adjust Constraints with the Chip Planner 1.1.2.4. Constraining Designs with the Design Partition Planner
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Intel® Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows
1.2.5. Tcl-only Script Flows x
1.2.5.1. Tcl-only Timing Analysis
2. Managing Device I/O Pins x
2.1. I/O Planning Overview 2.2. Assigning I/O Pins 2.3. Importing and Exporting I/O Pin Assignments 2.4. Validating Pin Assignments 2.5. Verifying I/O Timing 2.6. Viewing Routing and Timing Delays 2.7. Analyzing Simultaneous Switching Noise 2.8. Scripting API 2.9. Managing Device I/O Pins Revision History
2.1. I/O Planning Overview x
2.1.1. Basic I/O Planning Flow 2.1.2. Integrating PCB Design Tools 2.1.3. Intel Device Terms
2.2. Assigning I/O Pins x
2.2.1. Assigning to Exclusive Pin Groups 2.2.2. Assigning Slew Rate and Drive Strength 2.2.3. Assigning Differential Pins 2.2.4. Entering Pin Assignments with Tcl Commands 2.2.5. Entering Pin Assignments in HDL Code
2.2.3. Assigning Differential Pins x
2.2.3.1. Overriding I/O Placement Rules on Differential Pins
2.2.5. Entering Pin Assignments in HDL Code x
2.2.5.1. Using Synthesis Attributes 2.2.5.2. Using Low-Level I/O Primitives
2.3. Importing and Exporting I/O Pin Assignments x
2.3.1. Importing and Exporting for PCB Tools 2.3.2. Migrating Assignments to Another Target Device
2.4. Validating Pin Assignments x
2.4.1. I/O Assignment Validation Rules 2.4.2. Checking I/O Pin Assignments in Real-Time 2.4.3. I/O Assignment Analysis 2.4.4. Understanding I/O Analysis Reports
2.4.3. I/O Assignment Analysis x
2.4.3.1. Early I/O Assignment Analysis Without Design Files 2.4.3.2. I/O Assignment Analysis With Design Files 2.4.3.3. Overriding Default I/O Pin Analysis
2.5. Verifying I/O Timing x
2.5.1. Running Advanced I/O Timing 2.5.2. Adjusting I/O Timing and Power with Capacitive Loading
2.5.1. Running Advanced I/O Timing x
2.5.1.1. Board Trace Models 2.5.1.2. Defining the Board Trace Model 2.5.1.3. Modifying the Board Trace Model 2.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 2.5.1.5. Advanced I/O Timing Analysis Reports
2.8. Scripting API x
2.8.1. Generate Mapped Netlist 2.8.2. Reserve Pins 2.8.3. Set Location 2.8.4. Exclusive I/O Group 2.8.5. Slew Rate and Current Strength
1. Constraining Designs
2. Managing Device I/O Pins
A. Intel® Quartus® Prime Standard Edition User Guides

2.4.1. I/O Assignment Validation Rules

I/O Assignment Analysis validates your assignments against the following rules:

Table 8.  Examples of I/O Rule Checks
Rule Description HDL Required?

I/O bank capacity

Checks the number of pins assigned to an I/O bank against the number of pins allowed in the I/O bank.

No

I/O bank VCCIO voltage compatibility

Checks that no more than one VCCIO is required for the pins assigned to the I/O bank.

No

I/O bank VREF voltage compatibility

Checks that no more than one VREF is required for the pins assigned to the I/O bank.

No

I/O standard and location conflicts

Checks whether the pin location supports the assigned I/O standard.

No

I/O standard and signal direction conflicts

Checks whether the pin location supports the assigned I/O standard and direction. For example, certain I/O standards on a particular pin location can only support output pins.

No

Differential I/O standards cannot have open drain turned on

Checks that open drain is turned off for all pins with a differential I/O standard.

No

I/O standard and drive strength conflicts

Checks whether the drive strength assignments are within the specifications of the I/O standard.

No

Drive strength and location conflicts

Checks whether the pin location supports the assigned drive strength.

No

BUSHOLD and location conflicts

Checks whether the pin location supports BUSHOLD. For example, dedicated clock pins do not support BUSHOLD.

No

WEAK_PULLUP and location conflicts

Checks whether the pin location supports WEAK_PULLUP (for example, dedicated clock pins do not support WEAK_PULLUP).

No

Electromigration check

Checks whether combined drive strength of consecutive pads exceeds a certain limit. For example, the total current drive for 10 consecutive pads on a Stratix® II device cannot exceed 200 mA.

No

PCI_IO clamp diode, location, and I/O standard conflicts

Checks whether the pin location along with the I/O standard assigned supports PCI_IO clamp diode.

No

SERDES and I/O pin location compatibility check

Checks that all pins connected to a SERDES in your design are assigned to dedicated SERDES pin locations.

Yes

PLL and I/O pin location compatibility check

Checks whether pins connected to a PLL are assigned to the dedicated PLL pin locations.

Yes
Table 9.  Signal Switching Noise Rules
Rule Description HDL Required?

I/O bank cannot have single-ended I/O when DPA exists

Checks that no single-ended I/O pin exists in the same I/O bank as a DPA.

No

A PLL I/O bank does not support both a single-ended I/O and a differential signal simultaneously

Checks that there are no single-ended I/O pins present in the PLL I/O Bank when a differential signal exists.

No

Single-ended output is required to be a certain distance away from a differential I/O pin

Checks whether single-ended output pins are a certain distance away from a differential I/O pin.

No

Single-ended output must be a certain distance away from a VREF pad

Checks whether single-ended output pins are a certain distance away from a VREF pad.

No

Single-ended input is required to be a certain distance away from a differential I/O pin

Checks whether single-ended input pins are a certain distance away from a differential I/O pin.

No

Too many outputs or bidirectional pins in a VREFGROUP when a VREF is used

Checks that there are no more than a certain number of outputs or bidirectional pins in a VREFGROUP when a VREF is used.

No

Too many outputs in a VREFGROUP

Checks whether too many outputs are in a VREFGROUP.

No
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