Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

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ID 683492
Date 1/10/2019
Public
Document Table of Contents
Document Table of Contents x
1. Constraining Designs 2. Managing Device I/O Pins A. Intel® Quartus® Prime Standard Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints Designs in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints Designs in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Intel® Quartus® Prime GUI 1.1.4. Specifying Timing Constraints in the GUI
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify I/O Constraints in Pin Planner 1.1.2.3. Adjust Constraints with the Chip Planner 1.1.2.4. Constraining Designs with the Design Partition Planner
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Intel® Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows fir_filter_generated.tcl Tcl file
1.2.5. Tcl-only Script Flows x
fir_filter_generated.tcl Tcl file 1.2.5.1. Tcl-only Timing Analysis
2. Managing Device I/O Pins x
2.1. I/O Planning Overview 2.2. Assigning I/O Pins 2.3. Importing and Exporting I/O Pin Assignments 2.4. Validating Pin Assignments 2.5. Verifying I/O Timing 2.6. Viewing Routing and Timing Delays 2.7. Analyzing Simultaneous Switching Noise 2.8. Scripting API 2.9. Managing Device I/O Pins Revision History
2.1. I/O Planning Overview x
2.1.1. Basic I/O Planning Flow 2.1.2. Integrating PCB Design Tools 2.1.3. Intel Device Terms
2.2. Assigning I/O Pins x
2.2.1. Assigning to Exclusive Pin Groups 2.2.2. Assigning Slew Rate and Drive Strength 2.2.3. Assigning Differential Pins 2.2.4. Entering Pin Assignments with Tcl Commands 2.2.5. Entering Pin Assignments in HDL Code
2.2.3. Assigning Differential Pins x
2.2.3.1. Overriding I/O Placement Rules on Differential Pins
2.2.5. Entering Pin Assignments in HDL Code x
2.2.5.1. Using Synthesis Attributes 2.2.5.2. Using Low-Level I/O Primitives
2.3. Importing and Exporting I/O Pin Assignments x
2.3.1. Importing and Exporting for PCB Tools 2.3.2. Migrating Assignments to Another Target Device
2.4. Validating Pin Assignments x
2.4.1. I/O Assignment Validation Rules 2.4.2. Checking I/O Pin Assignments in Real-Time 2.4.3. I/O Assignment Analysis 2.4.4. Understanding I/O Analysis Reports
2.4.3. I/O Assignment Analysis x
2.4.3.1. Early I/O Assignment Analysis Without Design Files 2.4.3.2. I/O Assignment Analysis With Design Files 2.4.3.3. Overriding Default I/O Pin Analysis
2.5. Verifying I/O Timing x
2.5.1. Running Advanced I/O Timing 2.5.2. Adjusting I/O Timing and Power with Capacitive Loading
2.5.1. Running Advanced I/O Timing x
2.5.1.1. Board Trace Models 2.5.1.2. Defining the Board Trace Model 2.5.1.3. Modifying the Board Trace Model 2.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 2.5.1.5. Advanced I/O Timing Analysis Reports
2.8. Scripting API x
2.8.1. Generate Mapped Netlist 2.8.2. Reserve Pins 2.8.3. Set Location 2.8.4. Exclusive I/O Group 2.8.5. Slew Rate and Current Strength
1. Constraining Designs
2. Managing Device I/O Pins
A. Intel® Quartus® Prime Standard Edition User Guides

1.2.5. Tcl-only Script Flows

As an alternative to .sdc and .qsf files, you can perform all design assignments and timing constraints inside the Tcl scripts. In this case, the script that automates compilation and custom results reporting also contains the design constraints.

You can export a design's contents to a procedural, executable Tcl (.tcl) file, and then use the generated script to restore settings after experimenting with other constraints.

To export your constraints as an executable Tcl script, click Project > Generate Tcl File for Project.

fir_filter_generated.tcl Tcl file 

# Quartus Prime: Generate Tcl File for Project
# File: fir_filter_generated.tcl
# Generated on: Tue May  9 18:41:24 2017
# Load Quartus Prime Tcl Project package

package require ::quartus::project
set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
    if {[string compare $quartus(project) "fir_filter"]} {
      puts "Project fir_filter is not open"
      set make_assignments 0
      }
} else {
    # Only open if not already open
    if {[project_exists fir_filter]} {
      project_open -revision filtref fir_filter
    } else {
      project_new -revision filtref fir_filter
    }
    set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
	set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:37:10  MAY 7, 2009"
	set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
	set_global_assignment -name VERILOG_FILE mult.v
	set_global_assignment -name VERILOG_FILE accum.v
	set_global_assignment -name BDF_FILE filtref.bdf
	set_global_assignment -name VERILOG_FILE hvalues.v
	set_global_assignment -name VERILOG_FILE taps.v
	set_global_assignment -name VERILOG_FILE state_m.v
	set_global_assignment -name VERILOG_FILE acc.v
	set_global_assignment -name SMART_RECOMPILE ON
	set_global_assignment -name VECTOR_WAVEFORM_FILE fir.vwf
	set_global_assignment -name FMAX_REQUIREMENT "85 MHz"
	set_global_assignment -name FAMILY "Cyclone IV GX"
	set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
	set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
	set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
	set_global_assignment -name MUX_RESTRUCTURE OFF
	set_global_assignment -name DEVICE EP4CGX15BF14C6
	set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
	set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
	set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
	set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
	set_global_assignment -name VECTOR_INPUT_SOURCE fir.vwf
	set_global_assignment -name BASED_ON_CLOCK_SETTINGS clocka -section_id clockb
	set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 2 -section_id clockb
	set_global_assignment -name OFFSET_FROM_BASE_CLOCK "500 ps" -section_id clockb
	set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id clocka
	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
	set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
	set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
	set_location_assignment PIN_F13 -to reset
	set_location_assignment PIN_G10 -to d[2]
	set_location_assignment PIN_F12 -to clk
	set_location_assignment PIN_A10 -to clkx2
	set_location_assignment PIN_G9 -to d[1]
	set_location_assignment PIN_C12 -to d[7]
	set_location_assignment PIN_F10 -to follow
	set_location_assignment PIN_F9 -to yvalid
	set_location_assignment PIN_E13 -to yn_out[2]
	set_location_assignment PIN_E10 -to yn_out[3]
	set_location_assignment PIN_C11 -to d[4]
	set_location_assignment PIN_F11 -to d[0]
	set_location_assignment PIN_C13 -to d[6]
	set_location_assignment PIN_C8 -to yn_out[6]
	set_location_assignment PIN_B13 -to d[5]
	set_location_assignment PIN_B11 -to d[3]
	set_location_assignment PIN_B10 -to yn_out[5]
	set_location_assignment PIN_B8 -to yn_out[0]
	set_location_assignment PIN_A13 -to yn_out[7]
	set_location_assignment PIN_A11 -to yn_out[4]
	set_location_assignment PIN_A12 -to yn_out[1]
	set_location_assignment PIN_A9 -to newt
	set_instance_assignment -name CLOCK_SETTINGS clocka -to clk
	set_instance_assignment -name CLOCK_SETTINGS clockb -to clkx2
	set_instance_assignment -name MULTICYCLE 2 -from clk -to clkx2
	set_instance_assignment -name SLEW_RATE 2 -to yvalid
	set_instance_assignment -name SLEW_RATE 2 -to yn_out[0]
	set_instance_assignment -name SLEW_RATE 2 -to follow
	set_instance_assignment -name SLEW_RATE 2 -to yn_out[7]
	set_instance_assignment -name SLEW_RATE 2 -to yn_out[6]
	set_instance_assignment -name SLEW_RATE 2 -to yn_out[5]
	set_instance_assignment -name SLEW_RATE 2 -to yn_out[4]
	set_instance_assignment -name SLEW_RATE 2 -to yn_out[3]
	set_instance_assignment -name SLEW_RATE 2 -to yn_out[2]
	set_instance_assignment -name SLEW_RATE 2 -to yn_out[1]
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to follow
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[7]
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[6]
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[5]
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[4]
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[3]
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[2]
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[1]
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[0]
	set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yvalid
	set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

    # Commit assignments
    export_assignments
    
    # Close project
    if {$need_to_close_project} {
      project_close
    }
}

The example:

  • Opens the project
  • Assigns Constraints
  • Writes assignments to QSF file
  • Closes project

Section Content
Tcl-only Timing Analysis

Level Two Title