Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

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ID 683492
Date 1/10/2019
Public
Document Table of Contents
Document Table of Contents x
1. Constraining Designs 2. Managing Device I/O Pins A. Intel® Quartus® Prime Standard Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints Designs in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints Designs in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Intel® Quartus® Prime GUI 1.1.4. Specifying Timing Constraints in the GUI
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify I/O Constraints in Pin Planner 1.1.2.3. Adjust Constraints with the Chip Planner 1.1.2.4. Constraining Designs with the Design Partition Planner
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Intel® Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files 1.2.5. Tcl-only Script Flows
1.2.5. Tcl-only Script Flows x
1.2.5.1. Tcl-only Timing Analysis
2. Managing Device I/O Pins x
2.1. I/O Planning Overview 2.2. Assigning I/O Pins 2.3. Importing and Exporting I/O Pin Assignments 2.4. Validating Pin Assignments 2.5. Verifying I/O Timing 2.6. Viewing Routing and Timing Delays 2.7. Analyzing Simultaneous Switching Noise 2.8. Scripting API 2.9. Managing Device I/O Pins Revision History
2.1. I/O Planning Overview x
2.1.1. Basic I/O Planning Flow 2.1.2. Integrating PCB Design Tools 2.1.3. Intel Device Terms
2.2. Assigning I/O Pins x
2.2.1. Assigning to Exclusive Pin Groups 2.2.2. Assigning Slew Rate and Drive Strength 2.2.3. Assigning Differential Pins 2.2.4. Entering Pin Assignments with Tcl Commands 2.2.5. Entering Pin Assignments in HDL Code
2.2.3. Assigning Differential Pins x
2.2.3.1. Overriding I/O Placement Rules on Differential Pins
2.2.5. Entering Pin Assignments in HDL Code x
2.2.5.1. Using Synthesis Attributes 2.2.5.2. Using Low-Level I/O Primitives
2.3. Importing and Exporting I/O Pin Assignments x
2.3.1. Importing and Exporting for PCB Tools 2.3.2. Migrating Assignments to Another Target Device
2.4. Validating Pin Assignments x
2.4.1. I/O Assignment Validation Rules 2.4.2. Checking I/O Pin Assignments in Real-Time 2.4.3. I/O Assignment Analysis 2.4.4. Understanding I/O Analysis Reports
2.4.3. I/O Assignment Analysis x
2.4.3.1. Early I/O Assignment Analysis Without Design Files 2.4.3.2. I/O Assignment Analysis With Design Files 2.4.3.3. Overriding Default I/O Pin Analysis
2.5. Verifying I/O Timing x
2.5.1. Running Advanced I/O Timing 2.5.2. Adjusting I/O Timing and Power with Capacitive Loading
2.5.1. Running Advanced I/O Timing x
2.5.1.1. Board Trace Models 2.5.1.2. Defining the Board Trace Model 2.5.1.3. Modifying the Board Trace Model 2.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 2.5.1.5. Advanced I/O Timing Analysis Reports
2.8. Scripting API x
2.8.1. Generate Mapped Netlist 2.8.2. Reserve Pins 2.8.3. Set Location 2.8.4. Exclusive I/O Group 2.8.5. Slew Rate and Current Strength
1. Constraining Designs
2. Managing Device I/O Pins
A. Intel® Quartus® Prime Standard Edition User Guides

2.1. I/O Planning Overview

On FPGA design, I/O planning includes creating pin-related assignments and validating them against pin placement guidelines. This process ensures a successful fit in your target device. When you plan and assign I/O pins in the initial stages of your project, you design for compatibility with your target device and PCB characteristics. As a result, your design process goes through fewer iterations, and you develop an accurate PCB layout sooner.

You can plan your I/O pins even before defining design files. Assign expected nodes not yet defined in design files, including interface IP core signals, and then generate a top-level file. The top-level file instantiates the next level of design hierarchy and includes interface port information like memory, high-speed I/O, device configuration, and debugging tools.

Assign design elements, I/O standards, interface IP, and other properties to the device I/O pins by name or by dragging to cells. You can then generate a top-level design file for I/O validation.

Use I/O assignment validation to fully analyze I/O pins against VCCIO, VREF, electromigration (current density), Simultaneous Switching Output (SSO), drive strength, I/O standard, PCI_IO clamp diode, and I/O pin direction compatibility rules.

Intel® Quartus® Prime software provides the Pin Planner tool to view, assign, and validate device I/O pin logic and properties. Alternatively, you can enter I/O assignments in a Tcl script, or directly in HDL code.


Section Content
Basic I/O Planning Flow
Integrating PCB Design Tools
Intel Device Terms

Level Two Title