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2.1. I/O Planning Overview
2.2. Assigning I/O Pins
2.3. Importing and Exporting I/O Pin Assignments
2.4. Validating Pin Assignments
2.5. Verifying I/O Timing
2.6. Viewing Routing and Timing Delays
2.7. Analyzing Simultaneous Switching Noise
2.8. Scripting API
2.9. Managing Device I/O Pins Revision History
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Ixiasoft
1.2.4. Synopsys* Design Constraint (.sdc) Files
Intel® Quartus® Prime software keeps timing constraints in .sdc files, which use Tcl syntax. You can embed these constraints in a scripted compilation flow, and even create sets of .sdc files for timing optimization.
.sdc File
The example shows the timing constrains of a small design.
## PROGRAM "Quartus Prime" ## VERSION "Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition" ## DATE "Wed May 10 14:03:25 2017" ## ## DEVICE "EP4CGX15BF14C6" ## #************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {clk} -period 4.000 -waveform { 0.000 2.000 } [get_ports {clk}] create_clock -name {clkx2} -period 4.000 -waveform { 0.000 2.000 } [get_ports {clkx2}] #************************************************************** # Set Clock Uncertainty #************************************************************** set_clock_uncertainty -rise_from [get_clocks {clkx2}] -rise_to [get_clocks {clkx2}] 0.020 set_clock_uncertainty -rise_from [get_clocks {clkx2}] -fall_to [get_clocks {clkx2}] 0.020 set_clock_uncertainty -fall_from [get_clocks {clkx2}] -rise_to [get_clocks {clkx2}] 0.020 set_clock_uncertainty -fall_from [get_clocks {clkx2}] -fall_to [get_clocks {clkx2}] 0.020 set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clkx2}] 0.040 set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clkx2}] 0.040 set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] 0.020 set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] 0.020 set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clkx2}] 0.040 set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clkx2}] 0.040 set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] 0.020 set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] 0.020 #************************************************************** # Set False Path #************************************************************** set_false_path -from [get_clocks {clk clkx2}] -through [get_pins -compatibility_mode *] -to [get_clocks {clk clkx2}]
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