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2.1. I/O Planning Overview
2.2. Assigning I/O Pins
2.3. Importing and Exporting I/O Pin Assignments
2.4. Validating Pin Assignments
2.5. Verifying I/O Timing
2.6. Viewing Routing and Timing Delays
2.7. Analyzing Simultaneous Switching Noise
2.8. Scripting API
2.9. Managing Device I/O Pins Revision History
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1.2.3. Generating Intel® Quartus® Prime Settings Files
Intel® Quartus® Prime software allows you to generate .qsf files from your revision. You can embed these constraints in a scripted compilation flow, and even create sets of .qsf files for design optimization.
To generate a .qsf file from the Intel® Quartus® Prime software, click Assignments > Export Assignments.
To organize the .qsf in a human readable form, Project > Organize Intel® Quartus® Prime Settings File.
Organized .qsf File
This example shows how .qsf files characterize a design revision. The set_global_assignment command makes all global constraints and software settings and set_location_assignment constrains each I/O node in the design to a physical pin on the device.
# Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:37:10 MAY 7, 2009" set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition" set_global_assignment -name VERILOG_FILE mult.v set_global_assignment -name VERILOG_FILE accum.v set_global_assignment -name BDF_FILE filtref.bdf set_global_assignment -name VERILOG_FILE hvalues.v set_global_assignment -name VERILOG_FILE taps.v set_global_assignment -name VERILOG_FILE state_m.v set_global_assignment -name VERILOG_FILE acc.v set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name VECTOR_WAVEFORM_FILE fir.vwf # Pin & Location Assignments # ========================== set_location_assignment PIN_F13 -to reset set_location_assignment PIN_G10 -to d[2] set_location_assignment PIN_F12 -to clk set_location_assignment PIN_A10 -to clkx2 set_location_assignment PIN_G9 -to d[1] set_location_assignment PIN_C12 -to d[7] set_location_assignment PIN_F10 -to follow set_location_assignment PIN_F9 -to yvalid set_location_assignment PIN_E13 -to yn_out[2] set_location_assignment PIN_E10 -to yn_out[3] set_location_assignment PIN_C11 -to d[4] set_location_assignment PIN_F11 -to d[0] set_location_assignment PIN_C13 -to d[6] set_location_assignment PIN_C8 -to yn_out[6] set_location_assignment PIN_B13 -to d[5] set_location_assignment PIN_B11 -to d[3] set_location_assignment PIN_B10 -to yn_out[5] set_location_assignment PIN_B8 -to yn_out[0] set_location_assignment PIN_A13 -to yn_out[7] set_location_assignment PIN_A11 -to yn_out[4] set_location_assignment PIN_A12 -to yn_out[1] set_location_assignment PIN_A9 -to newt # Classic Timing Assignments # ========================== set_global_assignment -name FMAX_REQUIREMENT "85 MHz" # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY "Cyclone IV GX" set_global_assignment -name TOP_LEVEL_ENTITY filtref set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name MUX_RESTRUCTURE OFF # Fitter Assignments # ================== set_global_assignment -name DEVICE EP4CGX15BF14C6 set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" # Simulator Assignments # ===================== set_global_assignment -name VECTOR_INPUT_SOURCE fir.vwf # start CLOCK(clockb) # ------------------- # Classic Timing Assignments # ========================== set_global_assignment -name BASED_ON_CLOCK_SETTINGS clocka -section_id clockb set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 2 -section_id clockb set_global_assignment -name OFFSET_FROM_BASE_CLOCK "500 ps" -section_id clockb # end CLOCK(clockb) # ----------------- # start CLOCK(clocka) # ------------------- # Classic Timing Assignments # ========================== set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id clocka # end CLOCK(clocka) # ----------------- # --------------------- # start ENTITY(filtref) # Classic Timing Assignments # ========================== set_instance_assignment -name CLOCK_SETTINGS clocka -to clk set_instance_assignment -name CLOCK_SETTINGS clockb -to clkx2 set_instance_assignment -name MULTICYCLE 2 -from clk -to clkx2 # Fitter Assignments # ================== set_instance_assignment -name SLEW_RATE 2 -to yvalid set_instance_assignment -name SLEW_RATE 2 -to yn_out[0] set_instance_assignment -name SLEW_RATE 2 -to follow set_instance_assignment -name SLEW_RATE 2 -to yn_out[7] set_instance_assignment -name SLEW_RATE 2 -to yn_out[6] set_instance_assignment -name SLEW_RATE 2 -to yn_out[5] set_instance_assignment -name SLEW_RATE 2 -to yn_out[4] set_instance_assignment -name SLEW_RATE 2 -to yn_out[3] set_instance_assignment -name SLEW_RATE 2 -to yn_out[2] set_instance_assignment -name SLEW_RATE 2 -to yn_out[1] set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to follow set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[7] set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[6] set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[5] set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[4] set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[3] set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[2] set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[1] set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yn_out[0] set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to yvalid # start DESIGN_PARTITION(Top) # --------------------------- # Incremental Compilation Assignments # =================================== set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(filtref) # ------------------- set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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