Intel® Quartus® Prime Standard Edition User Guide: Design Constraints

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ID 683492
Date 1/10/2019
Public
Document Table of Contents
Document Table of Contents x
1. Constraining Designs 2. Managing Device I/O Pins A. Intel® Quartus® Prime Standard Edition User Guides
1. Constraining Designs x
1.1. Specifying Design Constraints Designs in the GUI 1.2. Constraining Designs with Tcl Scripts 1.3. A Fully Iterative Scripted Flow 1.4. Constraining Designs Revision History
1.1. Specifying Design Constraints Designs in the GUI x
1.1.1. Global Constraints and Assignments 1.1.2. Node, Entity, and Instance-Level Constraints 1.1.3. Probing Between Components of the Intel® Quartus® Prime GUI 1.1.4. Specifying Timing Constraints in the GUI
1.1.2. Node, Entity, and Instance-Level Constraints x
1.1.2.1. Specify Instance-Specific Constraints in Assignment Editor 1.1.2.2. Specify I/O Constraints in Pin Planner 1.1.2.3. Adjust Constraints with the Chip Planner 1.1.2.4. Constraining Designs with the Design Partition Planner
1.2. Constraining Designs with Tcl Scripts x
1.2.1. Create a Project and Apply Constraints 1.2.2. Assigning a Pin 1.2.3. Generating Intel® Quartus® Prime Settings Files 1.2.4. Synopsys* Design Constraint (.sdc) Files .sdc File 1.2.5. Tcl-only Script Flows
1.2.5. Tcl-only Script Flows x
1.2.5.1. Tcl-only Timing Analysis
2. Managing Device I/O Pins x
2.1. I/O Planning Overview 2.2. Assigning I/O Pins 2.3. Importing and Exporting I/O Pin Assignments 2.4. Validating Pin Assignments 2.5. Verifying I/O Timing 2.6. Viewing Routing and Timing Delays 2.7. Analyzing Simultaneous Switching Noise 2.8. Scripting API 2.9. Managing Device I/O Pins Revision History
2.1. I/O Planning Overview x
2.1.1. Basic I/O Planning Flow 2.1.2. Integrating PCB Design Tools 2.1.3. Intel Device Terms
2.2. Assigning I/O Pins x
2.2.1. Assigning to Exclusive Pin Groups 2.2.2. Assigning Slew Rate and Drive Strength 2.2.3. Assigning Differential Pins 2.2.4. Entering Pin Assignments with Tcl Commands 2.2.5. Entering Pin Assignments in HDL Code
2.2.3. Assigning Differential Pins x
2.2.3.1. Overriding I/O Placement Rules on Differential Pins
2.2.5. Entering Pin Assignments in HDL Code x
2.2.5.1. Using Synthesis Attributes 2.2.5.2. Using Low-Level I/O Primitives
2.3. Importing and Exporting I/O Pin Assignments x
2.3.1. Importing and Exporting for PCB Tools 2.3.2. Migrating Assignments to Another Target Device
2.4. Validating Pin Assignments x
2.4.1. I/O Assignment Validation Rules 2.4.2. Checking I/O Pin Assignments in Real-Time 2.4.3. I/O Assignment Analysis 2.4.4. Understanding I/O Analysis Reports
2.4.3. I/O Assignment Analysis x
2.4.3.1. Early I/O Assignment Analysis Without Design Files 2.4.3.2. I/O Assignment Analysis With Design Files 2.4.3.3. Overriding Default I/O Pin Analysis
2.5. Verifying I/O Timing x
2.5.1. Running Advanced I/O Timing 2.5.2. Adjusting I/O Timing and Power with Capacitive Loading
2.5.1. Running Advanced I/O Timing x
2.5.1.1. Board Trace Models 2.5.1.2. Defining the Board Trace Model 2.5.1.3. Modifying the Board Trace Model 2.5.1.4. Specifying Near-End vs Far-End I/O Timing Analysis 2.5.1.5. Advanced I/O Timing Analysis Reports
2.8. Scripting API x
2.8.1. Generate Mapped Netlist 2.8.2. Reserve Pins 2.8.3. Set Location 2.8.4. Exclusive I/O Group 2.8.5. Slew Rate and Current Strength
1. Constraining Designs
2. Managing Device I/O Pins
A. Intel® Quartus® Prime Standard Edition User Guides

1.2.4. Synopsys* Design Constraint (.sdc) Files

Intel® Quartus® Prime software keeps timing constraints in .sdc files, which use Tcl syntax. You can embed these constraints in a scripted compilation flow, and even create sets of .sdc files for timing optimization.

.sdc File

The example shows the timing constrains of a small design. 

## PROGRAM "Quartus Prime"
## VERSION "Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition"		
## DATE    "Wed May 10 14:03:25 2017"  		
##
## DEVICE  "EP4CGX15BF14C6"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3  		
#**************************************************************
# Create Clock
#************************************************************** 		
create_clock -name {clk} -period 4.000 -waveform { 0.000 2.000 } [get_ports {clk}]
create_clock -name {clkx2} -period 4.000 -waveform { 0.000 2.000 } [get_ports {clkx2}]
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {clkx2}] -rise_to [get_clocks {clkx2}]  0.020  
set_clock_uncertainty -rise_from [get_clocks {clkx2}] -fall_to [get_clocks {clkx2}]  0.020  
set_clock_uncertainty -fall_from [get_clocks {clkx2}] -rise_to [get_clocks {clkx2}]  0.020  
set_clock_uncertainty -fall_from [get_clocks {clkx2}] -fall_to [get_clocks {clkx2}]  0.020  
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clkx2}]  0.040  
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clkx2}]  0.040  
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}]  0.020  
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}]  0.020  
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clkx2}]  0.040  
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clkx2}]  0.040  
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}]  0.020  
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}]  0.020  
#**************************************************************
# Set False Path
#************************************************************** 		
set_false_path -from [get_clocks {clk clkx2}] -through [get_pins -compatibility_mode *]  -to [get_clocks {clk clkx2}]
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