Visible to Intel only — GUID: fxk1519990233256
Ixiasoft
Visible to Intel only — GUID: fxk1519990233256
Ixiasoft
2.11.14.2. Transceiver Reconfiguration Interfaces
Asserting the i_csr_rst_n signal resets all Ethernet control and status registers, including the statistics counters; while this reset is in process, the Ethernet reconfiguration interface does not respond.
Port Name | Width | Description |
---|---|---|
i_xcvr_reconfig_address |
19 | Address bus for transceiver control and status registers. |
i_xcvr_reconfig_write |
1 | Transceiver write signal. When asserted, writes data on the reconfiguration write data bus. |
i_xcvr_reconfig_read |
1 | Transceiver read signal. When asserted, starts a read cycle. |
i_xcvr_reconfig_writedata |
8 bits each lane | Transceiver write data bus. When asserted, presents transceiver data written on a write cycle. |
o_xcvr_reconfig_readdata |
8 bits each lane | Transceiver read data bus. When asserted, presents transceiver data read on a read cycle. |
o_xcvr_reconfig_waitrequest |
1 | Indicates the Avalon® memory-mapped interface interface is busy. The read or write cycle is only complete when this signal goes low. |