Visible to Intel only — GUID: zin1554878152597
Ixiasoft
Visible to Intel only — GUID: zin1554878152597
Ixiasoft
3.9.1.2. Soft Reset Sequencer
The soft reset sequencer block manages the digital reset sequence in the soft logic of the E-Tile CPRI PHY IP.
Reset Port/Register | Block | |||||||
---|---|---|---|---|---|---|---|---|
TX EMIB Interface | TX PCS | TX PMA Interface | RX EMIB Interface | RX PCS | RX PMA Interfaces | Hard CSR | Soft CSR | |
i_sl_csr_rst_n, soft_sys_rst 34 |
√ 35 |
√ |
√ |
√ |
√ |
√ |
√ 36 |
— |
i_sl_tx_rst_n, soft_tx_rst |
— |
√ |
√ |
— |
— |
— |
— |
— |
i_sl_rx_rst_n, soft_rx_rst |
— |
— |
— |
— |
√ |
— |
— |
— |
i_reconfig_reset | — | — | — | — | — | — | — | √ |
Reset Sequence
The following waveforms show the reset sequence using the i_sl_csr_rst_n, i_sl_tx_rst_n, and i_sl_rx_rst_n signals.
System Considerations
You should perform a system reset before beginning IP core operation, preferably by asserting the i_csr_rst_n and i_reconfig_reset signals together. The IP core implements the correct reset sequence to reset the entire IP core.
If you assert the transmit reset when the downstream receiver is already aligned, the receiver loses alignment. Before the downstream receiver loses lock, it might receive some malformed frames.
If you assert the receive reset while the upstream transmitter is sending packets, the packets in transit get corrupted.
For the CPRI data rates with RS-FEC variant, deasserting the master channel's the i_sl_csr_rst_n signal interrupts all slave channels.